A universal buffered interface for coupling multiple processors, memory units, and I/O interfaces to a common high-speed bus

Claim 2

Interface circuitry as set forth in Claim 1 wherein the local bus agents include at least one data processor node that includes a data processor.

Claim 3

Interface circuitry as set forth in Claim 1 wherein the local bus agents include a plurality of I/O processing means each of which is coupled to an associated communication channel.

Claim 4

Interface circuitry as set forth in Claim 1 wherein the local bus agents include a plurality of memory banks.

Claim 5

Interface circuitry as set forth in Claim 1 and further comprising: means, coupled to the first interface means, for arbitrating for access to the local bus; and means, coupled to the second interface means, for arbitrating for access to the global bus; wherein each of the arbitrating means operates in accordance with a round robin technique.

Claim 6

Interface circuitry as set forth in Claim 2 wherein each of data processing nodes includes: means for specifying at least one other data processing node for receiving an interrupt, the specifying means having an output coupled to the first interface means for providing the data processing node specification thereto as address information; wherein the control information includes information for specifying a type of address information, including a specification of a processor interrupt type of address information.

Claim 7

Interface circuitry as set forth in Claim 4 and further comprising means for generating and checking an error correction code for the data information.

Claim 8

Interface circuitry as set forth in Claim 1 and further comprising means for generating and checking parity information at least for the data information and for the address information.

Claim 9

Interface circuitry as set forth in Claim 1 wherein the control information includes information for specifying an identification of a data processing means that sourced associated data information or that requested that associated information be returned from global memory means.

Claim 10

Interface circuitry as set forth in Claim 9 wherein the local bus agents include a plurality of memory banks, and further comprising means for prohibiting access to a storage location within one of the memory banks except to an identified data processing means that requests that access to the storage location be prohibited.

Claim 11

Interface circuitry as set forth in Claim 10 and further including means for storing the identification of the requesting data processing means.

Claim 12

Interface circuitry as set forth in Claim 1 wherein the second interface means includes means for bypassing the input queue means when the input queue means is empty.

Claim 13

Interface circuitry as set forth in Claim 1 wherein the first interface means includes means for bypassing the output queue means when the output queue means is empty.

Claim 14

Interface circuitry as set forth in Claim 1 wherein the second interface means includes: means for transmitting a content of the output queue means to the global bus; means for receiving an indication that a global bus agent has accepted or has not accepted the transmission; and means, responsive to the receiving means receiving an indication that a global bus agent has not accepted the transmission, for causing the transmitting means to retransmit the content of the output queue means to the global bus.

Claim 15

Interface circuitry as set forth in Claim 1 wherein the second interface means includes: means, responsive to information received from the global bus, for determining if the information is directed to one of the local bus agents coupled to the first interface means; and means, responsive to the determination, for generating an indication on the global bus that the received information has been accepted or has not been accepted.

Claim 16

Interface circuitry as set forth in Claim 15 wherein the generating means is coupled to the input queue means and is responsive to a full condition thereof for generating an indication that the received information has not been accepted.

Claim 17

In a data processing system including a plurality of data processors that are coupled together by bus means having at least a first plurality of signal lines for conveying address information and a second plurality of signal lines for conveying control information, a method of communicating between data processors, comprising the steps of: for a data processor initiating a communication with at least one other data processor, setting a bit or bits in a data processor mask so as to identify at least one other data processor to be communicated with; setting a bus transaction identifier for indicating a data processor communication bus transaction; and transmitting the data processor mask over the bus means using the first plurality of signal lines and the bus transaction identifier over the bus means using at least some of the second plurality of signal lines; the method further including the steps of, receiving, from the bus means, the data processor mask from the first plurality of signal lines and the bus transaction identifier from the second plurality of signal lines; decoding the received data processor mask and the bus transaction identifier; and interrupting the identified data processor or data processors.

Claim 18

A method as set forth in Claim 17 wherein the plurality of data processors are organized as groups of data processors with the members of each group being coupled together by a local bus means, and wherein the groups of data processors are coupled together by a global bus means, wherein the step of transmitting includes the steps of: receiving from a local bus means, with bus interface means coupled between the local bus means and the global bus means, the data processor mask from the first plurality of signal lines and the bus transaction identifier from the second plurality of signal lines; arbitrating, with the bus interface means, for access to the global bus means; and transmitting the received data processor mask to global bus means address signal lines and the bus transaction identifier to global bus means control signal lines for reception by another bus interface means.

Claim 19

A multiprocessor data processing system, comprising: at least one group comprised of (n) computational data processor nodes each of which includes a data processor having private memory means coupled thereto, each of the (n) computational data processor nodes within a group being coupled together by a first local bus means; at least one communication data processor node including a data processor having private memory means coupled thereto, the at least one communication data processor node being coupled to data communication means by a second local bus means; at least one shared global memory comprised of (x) memory banks coupled together by a third local bus means; and a plurality of bus interface means individual ones of which are coupled between one of the local bus means and a global bus means; wherein each of the plurality of bus interface means includes, a plurality (y) of input queue means each having an input coupled to the global bus means for receiving and storing address information, control information, and data information therefrom, each of the input queue means having an output coupled to the associated one of the local bus means; and a plurality (z) of output queue means each having an input coupled to the associated one of the local bus means for receiving and storing address information, control information, and data information therefrom, each of the output queue means having an output coupled to the global bus means.

Claim 20

A multiprocessor data processing system as set forth in Claim 19 wherein (n = x = y = z).

Claim 21

A multiprocessor data processing system as set forth in Claim 19 wherein each of the bus interface means further comprises: means, coupled to the local bus means, for arbitrating for access to the local bus means; and means, coupled to the global bus means, for arbitrating for access to the global bus means; wherein each of the arbitrating means operates in accordance with a round robin technique.

Claim 22

A multiprocessor data processing system as set forth in Claim 19 wherein each of the data processor nodes further comprises: means for setting a data processor mask so as to identify at least one other data processor to be communicated with; means for setting a bus transaction identifier for indicating a data processor communication bus transaction; and means for transmitting the data processor mask to address signal lines of the local bus means and the bus transaction identifier to control signal lines of the local bus means.

Claim 23

A multiprocessor data processing system as set forth in Claim 22 and further comprising: means for receiving, from the address signal lines of each local bus means, a data processor mask, and from the control signal lines of each local bus means, a bus transaction identifier transmitted from another data processor node; means for decoding the received data processor mask and the bus transaction identifier; and means for interrupting the identified data processor or data processors.

Claim 24

A multiprocessor data processing system as set forth in Claim 19 wherein the bus interface means coupled to the third local bus means further comprises: means for generating an error correction code for data information received from the global bus means for transmission to the third local bus means; and means for checking the error correction code for data information received from the third local bus means for transmission to the global bus means.

Claim 25

A multiprocessor data processing system as set forth in Claim 19 wherein each of the bus interface means further comprises: means for generating parity information at least for the data information and for the address information transmitted to the global bus means; and means for checking parity information at least for the data information and for the address information received from the global bus means.

Claim 26

A multiprocessor data processing system as set forth in Claim 19 wherein: each of the plurality of input queue means and the plurality of output queue means includes address queue means, data queue means, and control queue means.

Claim 27

A multiprocessor data processing system as set forth in Claim 19 wherein the bus interface means coupled to the third local bus means further comprises: means for converting a stored address into a Row Address and into a Column Address; and means for applying the Row Address and the Column Address to a selected one of the memory banks.

Claim 28

A multiprocessor data processing system as set forth in Claim 19 wherein the bus interface means coupled to the third local bus means further comprises: means for storing a last received address from the global bus means; means for comparing a next received address to the stored address; and means for indicating to the selected memory bank that the previously applied Row Address is to be reused.

Claim 29

A multiprocessor data processing system as set forth in Claim 19 wherein the bus interface means coupled to the third local bus means further comprises: means, responsive to a signal indicating a number of memory banks installed within the system, and responsive to a signal indicating a memory interleave factor, for remapping an address received from the global bus means to correspond to memory addresses associated with the memory banks.

Claim 30

A multiprocessor data processing system as set forth in Claim 19 wherein the bus interface means coupled to the third local bus means further comprises: means for prohibiting access to a storage location within one of the memory banks except to an identified data processing means that requests that access to the storage location be prohibited.

Claim 31

A multiprocessor data processing system as set forth in Claim 19 wherein the bus interface means coupled to the first local bus means and to the second local bus means further comprises: means for bypassing the input queue means when the input queue means is empty.

Claim 32

A multiprocessor data processing system as set forth in Claim 19 wherein each of the bus interface means further comprises: means for bypassing the output queue means when the output queue means is empty.

Claim 33

A multiprocessor data processing system as set forth in Claim 19 wherein: for the bus interface means coupled to the first local bus means, each of the computational data processor nodes is coupled to an associated one of the input queue means and to an associated one of the output queue means; for the bus interface means coupled to the second local bus means, the at least one communication data processor node is coupled to one of the input queue means and to one of the output queue means, and the communication means is coupled to another one of the input queue means and to another one of the output queue means; and for the bus interface means coupled to the third local bus means, each of the memory banks is coupled to one of the input queue means and to one of the output queue means.

Claim 34

Interface circuitry for use in a data processing system, comprising: first interface means for coupling to address signal lines and control signal lines of a first bus and including means for receiving and for buffering the address signal lines and the control signal lines for a plurality of consecutive first bus transactions; and second interface means for coupling to data signal lines of the first bus, the data signal lines being organized as a plurality of M data units each comprised of N bytes, said second interface means being partitioned into M functional units each of which includes means for receiving and for buffering N bytes of one of the M data units for a plurality of consecutive first bus transactions; wherein said first interface means includes control means, responsive to the address signal lines and control signal lines, for generating a plurality of data path control signals, said data path control signal being coupled in common to said M functional units of said second interface means for controlling the operation thereof with respect to the received N bytes of each of said M data units.

Claim 35

Interface circuitry as set forth in Claim 34 wherein M equals eight and wherein N equals four.

Claim 36

Interface circuitry as set forth in Claim 34 wherein the first bus has a plurality of bus agents coupled thereto, wherein, said buffer means of said first interface means includes a plurality of first queue means for buffering address and control signals received from the first bus, each of said first queue means having an output coupled to a second bus; and each of said M functional units of said second interface means includes a plurality of second queue means each of which buffers N bytes of data received from the first bus, each of the second queue means having an output coupled to the second bus; and wherein individual ones of the bus agents each have an individual one of the first queue means and an individual one of the second queue means dedicated thereto.

Claim 37

Interface circuitry as set forth in Claim 36 wherein the bus agents include at least one data processor node that includes a data processor.

Claim 38

Interface circuitry as set forth in Claim 36 wherein the bus agents include a plurality of I/O processing means each of which is coupled to an associated communication channel.

Claim 39

Interface circuitry as set forth in Claim 35 wherein the bus agents include a plurality of memory banks.

Claim 40

Interface circuitry as set forth in Claim 39 wherein said control signal lines include a signal line for indicating a read-modify-write type of memory operation and further include M times N byte enable signal lines, wherein each of said second interface means has N of the byte enable signal lines coupled thereto, and wherein each of said second interface means includes means, responsive to said data path control signals, for reading N bytes of data from a selected one of said memory banks, for selectively merging, if required, N bytes of buffered data with the N bytes read from the selected memory bank, as a function of the state of the associated N byte enable signal lines, and for writing the N bytes of merged data back into the selected memory bank.