EP0520580A1
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EP
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Method and devices for testing ATM connections
Assignee: Alcatel Lucent SAS
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Filing: 1992-06-25
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Granted: —
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Expires: 2012-06-25
Abstract
Abstract The information part of the test cells has twice the same contents, including time indications, sequence number within a connection and connection number. The repetition of the contents occurs octet per octet in inverse form.
Inventors
- 👤 Johannes Anthonius Maria Van Tetering
- 👤 Frank Lodewijk Denissen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 17:03
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L1/00; H04L1/0078; H04L1/0083
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
51 words
Method for testing the characteristics of an ATM connection between two points of an ATM network, characterized in that a sequence of test cells is transmitted and tested, the information parts of said cells being built up in an appropriate way with the purpose of recognizing predetermined characteristics of the connection.
Claim 2
Dependent Claim
28 words
Method according to claim 1, characterized in that the information part of each test cell comprises two parts, the second part being the inverse of the first one.
Claim 3
Dependent Claim
35 words
Method according to claim 2, characterized in that both parts are interwoven in such a way that each octet of the first part is immediately followed by the associated inversed octet of the second part.
Claim 4
Dependent Claim
68 words
Method according to claim 1, characterized in that each information part includes at least a time indication of the transmission time (TS), a sequence number (SN) in the ATM connection and a connection number (ID), these information being in inverse form or not and that the rest of the information including none of these data contains an indication (FL) that said data are in inverse form or not.
Claim 5
Dependent Claim
45 words
Test cell generator with devices for generating the data sequence of an ATM test cell, characterized in that the devices are executed in such a way that the data sequence may selectively, and at least piecewise, be generated in not-inverse form or in inverse form.
Claim 6
Dependent Claim
26 words
Test cell generator according to claim 5, characterized in that the data sequence is realized under the form of octets and is possibly inverted per octet.
Claim 7
Dependent Claim
48 words
Test cell generator according to claim 6, characterized in that the devices include : a clock circuit (LT) controlled by the cell clock (CCL), a connection number generator (ID), a write and read memory (MEM), a control circuit (TCGC), a switcheable inverter (INV) and an output register (REG).
Claim 8
Dependent Claim
50 words
Test cell generator according to claim 7, characterized in that the clock circuit (LT), the connection number generator (ID) and the write and read memory (MEM) are all coupled with the output register (REG) via an inverter (INV) and that all these units are controlled by the control circuit (TCGC).
Claim 9
Dependent Claim
59 words
Test cell generator according to claim 8, characterized in that it produces test cells the information part of which at least includes: a time indication (TS) of the sending time, a sequence number (SN) in an ATM connection and a connection number (ID) provided by the clock circuit (LT), the memory (MEM) and the connection number generator (ID) respectively.
Claim 10
Dependent Claim
21 words
Test cell generator according to claim 8, characterized in that said memory (MEM) also generates the headers of the test cells.
Claim 11
Dependent Claim
46 words
Evaluation circuit for testing ATM test cells, characterized in that it includes a cell header recognition circuit (HIDC) which by comparing the cell with a test cell is able to find out if an incoming cell is destined to the evaluation circuit (CELC REC) or not.
Claim 12
Dependent Claim
44 words
Evaluation circuit according to claim 11, characterized in that the data of the test cell are inverted octet per octet and that there is provided a circuit (TYPD) to find out if the data received are first non inverted and then inverted or vice-versa.
Claim 13
Dependent Claim
51 words
Evaluation circuit according to claim 11, characterized in that the test cells include a time indication (TS) of the sending time and that there is provided a circuit (DELC) to extract said time indication (TS) from a test cell and to calculate the difference thereof with a local time indication (LCTI).
Claim 14
Dependent Claim
90 words
Evaluation circuit according to claim 11, characterized in that the cells are provided with a header (H) with a first cell indication (PT) which is activated when a test or maintenance cell and not a data cell is concerned, and that these cells moreover contain an information part including a said cell indication (MCT, MCT ¯ ) which is activated when a test cell is concerned, a time indication (TS) of the sending time of the cell, a sequence number (SN) in an ATM connection and a connection number (ID).
Claim 15
Dependent Claim
78 words
Evaluation circuit according to claim 14, characterized in that said cell header recognition circuit (HIDC) compares the header of an incoming cell with that of a reference cell and that when these headers are equal and the first cell indication (PT) is activated it moreover compares the second cell indications (MCT, MCT ¯ ) and in case they are equal provides a first output signal (CELL REC) which indicates that the cell is destined to the evaluation circuit.
Claim 16
Dependent Claim
34 words
Evaluation circuit according to claim 15, characterized in that said first output signal (CELL REC) is also activated when the compared headers are equal, but when the first cell indications (PT) are not activated.
Claim 17
Dependent Claim
79 words
Evaluation circuit according to claim 15 or 16, characterized in that the cell header recognition circuit when the first output signal (CELL REC) is activated also compares the connection number (ID) of the incoming cell with that of the reference cell and generates an activated second output signal (CELL INS) when these connection numbers are different and there are no errors in the connection number of the incoming cell, said activated second output signal (CELL INS) indicating an error.
Claim 18
Dependent Claim
36 words
Evaluation circuit according to claim 11, characterized in that it includes an error recognition circuit (ERRC) to detect and correct bit errors, the result of this count being indicated by a third output signal (ERR PAT).
Claim 19
Dependent Claim
39 words
Evaluation circuit according to claims 14 and 18, characterized in that said error recognition circuit (ERRC) also checks the bit errors in an incoming connection number and upon detection of an error activates a fourth output signal (ERR ID).
Claim 20
Dependent Claim
47 words
Evaluation circuit according to claims 17 and 19, characterized in that the second output signal (CELL INS) is activated when the first output signal (CELL REC) and the fourth output signal (ERR ID) are activated and when the third output signal (ERR PAT) exceeds a predetermined threshold.
References Cited (Backward Citations)
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