EP0520470A2
Expired / Lapsed
EP
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Output circuit and semiconductor integrated circuit device
Assignee: Kyushu Fujitsu Electronics Ltd
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Filing: 1992-06-26
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Granted: —
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Expires: 2012-06-26
Abstract
Abstract The present invention relates to an output circuit and a semiconductor integrated circuit. It is an object of the present invention to cut off a passage of a current including a forward parasitic diode of a transistor connected to a power supply line and a ground line as a path at time of suspension of output operation of the relevant circuit, and to raise an output high level to the utmost and lower an output low level to the utmost at time of normal output operation. A complementary MOS high impedance output circuit composed of a first field effect transistor (TN1) and a second field effect transistor (TN2) both of one conductive type is structured so as to include provision of a third field effect transistor (TN3) for controlling one of a state of a backgate (BG1) of the first field effect transistor (TN1) and a state of a backgate (BG2) of the second field effect transistor (TN2) and also to include provision of a fourth field effect transistor (TN4) for controlling one of the state of the backgate (BG1, BG2) of the first and second field effect transistors (TN1, TN2) complementarily to the control of the state of the backgate (BG3) of the third field effect transistor (TN3).
Inventors
- 👤 Shouichi c/o Kyushu Fujitsu El. Ltd. Tanigashira
- 👤 Fumitaka c/o Fujitsu Limited Asami
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 22:35
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0013; H03K19/003; H03K19/00315; H03K19/00346; H03K19/00361; H03K2217/00; H03K2217/0018
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
127 words
An output circuit in which a first field effect transistor (TN1) of one conductive type and a second field effect transistor (TN2) of one conductive type are connected in series with each other between a first power supply line and a second power supply line, a drain junction of the first field effect transistor (TN1) and the second field effect transistor (TN2) is connected to an output terminal and complementary signals are inputted to gates of said first field effect transistor (TN1) and said second field effect transistor (TN2), comprising a third field effect transistor (TN3) for controlling one of a state of a backgate (BG1) of said first field effect transistor (TN1) and a state of a backgate (BG2) of said second field effect transistor (TN2).
Claim 2
Dependent Claim
103 words
An output circuit according to claim 1, wherein: said first, second and third field effect transistors are composed of n-type field effect transistors; said third field effect transistor is connected between the backgate of said first field effect transistor and said output terminal; a gate of said third field effect transistor is connected to a first power supply line; a backgate of said third field effect transistor is connected to one of a second power supply line and the backgate of said first field effect transistor; and a backgate of said second field effect transistor is connected to the second power supply line.
Claim 3
Dependent Claim
106 words
An output circuit according to claim 1, wherein: said first, second and third field effect transistors are composed of n-type field effect transistors; said third field effect transistor is connected between the backgate of said first field effect transistor and said output terminal; the gate of said third field effect transistor is connected to a gate of said first field effect transistor; the backgate of said third field effect transistor is connected to one of a second power supply line and the backgate of said first field effect transistor; and the backgate of said second field effect transistor is connected to the second power supply line.
Claim 4
Dependent Claim
103 words
An output circuit according to Claim 1, wherein: said first, second and third field effect transistors are composed of p-type field effect transistors; said backgate of said first field effect transistor is connected to the first power supply line; the third field effect transistor is connected between the backgate of said second field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the second power supply line; and the backgate of said third field effect transistor is connected to one of the first power supply line and the backgate of said second field effect transistor.
Claim 5
Dependent Claim
106 words
An output circuit according to Claim 1, wherein: said first, second and third field effect transistors are composed of p-type field effect transistors; said backgate of said first field effect transistor is connected to the first power supply line; the third field effect transistor is connected between the backgate of said second field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the gate of said second field effect transistor; and the backgate of said third field effect transistor is connected to one of the first power supply line and the backgate of said second field effect transistor.
Claim 6
Dependent Claim
136 words
An output circuit in which an n-type first field effect transistor and a p-type second field effect transistor are connected in series with each other, said first field effect transistor is connected to a first power supply line on a high potential side, said second field effect transistor is connected to a second power supply line on a low potential side, a drain junction of said n-type first field effect transistor and said p-type second field effect transistor is connected to an output terminal, and identical signals are inputted to gates of said first field effect transistor and said second field effect transistor, comprising a third field effect transistor for controlling one of a state of a backgate of said first field effect transistor and a state of a backgate of said second field effect transistor.
Claim 7
Dependent Claim
113 words
An output circuit according to Claim 6, wherein: said first and third field effect transistors are composed of n-type field effect transistors; said second field effect transistor is composed of a p-type field effect transistor; said third field effect transistor is connected between the backgate of said first field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the first power supply line; the backgate of said third field effect transistor is connected to one of the second power supply line and the backgate of said first field effect transistor; and the backgate of said second field effect transistor is connected to said output terminal.
Claim 8
Dependent Claim
116 words
An output circuit according to Claim 6, wherein: said first and third field effect transistors are composed of n-type field effect transistors; said second field effect transistor is composed of a p-type field effect transistor; said third field effect transistor is connected between the backgate of said first field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the gate of said first field effect transistor; the backgate of said third field effect transistor is connected to one of the second power supply line and the backgate of said first field effect transistor; and the backgate of said second field effect transistor is connected to said output terminal.
Claim 9
Dependent Claim
113 words
An output circuit according to Claim 6, wherein: said first field effect transistor is composed of an n-type field effect transistor; said second and third field effect transistors are composed of p-type field effect transistors; said backgate of said first field effect transistor is connected to said output terminal; the third field effect transistor is connected between the backgate of said second field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the second power supply line; and the backgate of said third field effect transistor is connected to one of the first power supply line and the backgate of said second field effect transistor.
Claim 10
Dependent Claim
116 words
An output circuit according to Claim 6, wherein: said first field effect transistor is composed of an n-type field effect transistor; said second and third field effect transistors are composed of p-type field effect transistors: said backgate of said first field effect transistor is connected to said output terminal; the third field effect transistor is connected between the backgate of said second field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the gate of said second field effect transistor; and the backgate of said third field effect transistor is connected to one of the first power supply line and the backgate of said second field effect transistor.
Claim 11
Dependent Claim
155 words
An output circuit in which a first field effect transistor of one conductive type and a second field effect transistor of one conductive type are connected in series with each other between a first power supply line and a second power supply line, a drain junction of the first field effect transistor and the second field effect transistor is connected to an output terminal, and complementary signals are inputted to gates of said first field effect transistor and said second field effect transistor, comprising: a third field effect transistor for controlling one of the state of the backgate of said first field effect transistor and the state of the backgate of said second field effect transistor; and a fourth field effect transistor for controlling one of the state of the backgate of said first and second field effect transistor complementarily to the control of the state of the backgate of said third field effect transistor.
Claim 12
Dependent Claim
161 words
An output circuit according to Claim 11, wherein: said first, second, third and fourth field effect transistors are composed of n-type field effect transistors; said third field effect transistor is connected between the backgate of said first field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the first power supply line; the backgate of said third field effect transistor is connected to one of the second power supply line and the backgate of said first field effect transistor; the backgate of said second field effect transistor is connected to the second power supply line; said fourth field effect transistor is connected between the backgate of said first field effect transistor and said second power supply line; the backgate of said fourth field effect transistor is connected to the second power supply line; and the gate of said fourth field effect transistor is connected to the gate of the second field effect transistor.
Claim 13
Dependent Claim
164 words
An output circuit according to Claim 11, wherein: said first, second, third and fourth field effect transistors are composed of n-type field effect transistors; said third field effect transistor is connected between the backgate of said first field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the gate of said first field effect transistor; the backgate of said third field effect transistor is connected to one of the second power supply line and the backgate of said first field effect transistor; the backgate of said second field effect transistor is connected to the second power supply line; said fourth field effect transistor is connected between the backgate of said first field effect transistor and said second power supply line; the backgate of said fourth field effect transistor is connected to the second power supply line; and the gate of said fourth field effect transistor is connected to the gate of the second field effect transistor.
Claim 14
Dependent Claim
176 words
An output circuit according to Claim 11, wherein: said first, second, third and fourth field effect transistors are composed of p-type field effect transistors; said backgate of said first field effect transistor is connected to the first power supply line; the third field effect transistor is connected between the backgate of said second field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the second power supply line; the backgate of said third field effect transistor is connected to one of the first power supply line and the backgate of said second field effect transistor; said fourth field effect transistor is connected between the backgate of said second field effect transistor and said first power supply line; the gate of said fourth field effect transistor is connected to said signal inversion element; the backgate of said fourth field effect transistor is connected to the first power supply line; and the gate of said fourth field effect transistor is connected to the gate of the first field effect transistor.
Claim 15
Dependent Claim
164 words
An output circuit according to Claim 11, wherein: said first, second, third and fourth field effect transistors are composed of p-type field effect transistors; said backgate of said first field effect transistor is connected to the first power supply line; the third field effect transistor is connected between the backgate of said second field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the gate of said second field effect transistor; the backgate of said third field effect transistor is connected to one of the first power supply line and the backgate of said second field effect transistor; said fourth field effect transistor is connected between the backgate of said second field effect transistor and said first power supply line; the backgate of said fourth field effect transistor is connected to the first power supply line; and the gate of said fourth field effect transistor is connected to the gate of the first field effect transistor.
Claim 16
Dependent Claim
175 words
An output circuit in which an n-type first field effect transistor and a p-type second field effect transistor are connected in series with each other, said first field effect transistor is connected to a first power supply line on a high potential side, said second field effect transistor is connected to a second power supply line on a low potential side, a drain junction of said n-type first field effect transistor and said p-type second field effect transistor is connected to an output terminal, and identical signals are inputted to gates of said first field effect transistor and said second field effect transistor, comprising: a third field effect transistor for controlling one of the state of the backgate of said first field effect transistor and the state of the backgate of said second field effect transistor; and a fourth field effect transistor for controlling one of the state of the backgate of said first and second field effect transistor complementarily to the control of the state of the backgate of said third field effect transistor.
Claim 17
Dependent Claim
172 words
An output circuit according to Claim 16, wherein: said first, third and fourth field effect transistors are composed of n-type field effect transistors; said second field effect transistor is composed of a p-type field effect transistor; said third field effect transistor is connected between the backgate of said first field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the first power supply line; the backgate of said third field effect transistor is connected to one of the second power supply line and the backgate of said first field effect transistor; the backgate of said second field effect transistor is connected to said output terminal; said fourth field effect transistor is connected between the backgate of said first field effect transistor and said second power supply line; the backgate of said fourth field effect transistor is connected to the second power supply line; and an inversion signal of the first field effect transistor is inputted to the gate of said fourth field effect transistor.
Claim 18
Dependent Claim
190 words
An output circuit according to Claim 16, wherein: said first, third and fourth field effect transistors are composed of n-type field effect transistors; said second field effect transistor is composed of a p-type field effect transistor; said third field effect transistor is connected between the backgate of said first field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the gate of said first field effect transistor; the backgate of said third field effect transistor is connected to one of the second power supply line and the backgate of said first field effect transistor; the backgate of said second field effect transistor is connected to said output terminal; said fourth field effect transistor is connected between the backgate of said first field effect transistor and said second power supply line; the gate of said fourth field effect transistor is connected to said signal inversion element; the backgate of said fourth field effect transistor is connected to the second power supply line; and an inversion signal of the first field effect transistor is inputted to the gate of said fourth field effect transistor.
Claim 19
Dependent Claim
172 words
An output circuit according to Claim 16, wherein: said first field effect transistors is composed of an n-type field effect transistor; said second, third and fourth field effect transistors are composed of p-type field effect transistors; said backgate of said first field effect transistor is connected to said output terminal; the third field effect transistor is connected between the backgate of said second field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the second power supply line; the backgate of said third field effect transistor is connected to one of the first power supply line and the backgate of said second field effect transistor; said fourth field effect transistor is connected between the backgate of said second field effect transistor and said first power supply line; the backgate of said fourth field effect transistor is connected to the first power supply line; and an inversion signal of the first field effect transistor is inputted to the gate of said fourth field effect transistor.
Claim 20
Dependent Claim
175 words
An output circuit according to Claim 16, wherein: said first field effect transistor is composed of an n-type field effect transistor; said second, third and fourth field effect transistors are composed of p-type field effect transistors; said backgate of said first field effect transistor is connected to said output terminal; the third field effect transistor is connected between the backgate of said second field effect transistor and said output terminal; the gate of said third field effect transistor is connected to the gate of said second field effect transistor; the backgate of said third field effect transistor is connected to one of the first power supply line and the backgate of said second field effect transistor; said fourth field effect transistor is connected between the backgate of said second field effect transistor and said first power supply line; the backgate of said fourth field effect transistor is connected to the first power supply line; and an inversion signal of the first field effect transistor is inputted to the gate of said fourth field effect transistor.
Claim 21
Dependent Claim
52 words
A semiconductor integrated circuit characterized in that a complementary MOS high impedance output circuit is composed of an output circuit according to Claim 1, and a semiconductor integrated circuit device provided with a plurality of said complementary MOS high impedance output circuits is connected to a signal transmission line for common use.
Claim 22
Dependent Claim
52 words
A semiconductor integrated circuit characterized in that a complementary MOS high impedance output circuit is composed of an output circuit according to Claim 6, and a semiconductor integrated circuit device provided with a plurality of said complementary MOS high impedance output circuits is connected to a signal transmission line for common use.
Claim 23
Dependent Claim
52 words
A semiconductor integrated circuit characterized in that a complementary MOS high impedance output circuit is composed of an output circuit according to Claim 11, and a semiconductor integrated circuit device provided with a plurality of said complementary MOS high impedance output circuits is connected to a signal transmission line for common use.
Claim 24
Dependent Claim
52 words
A semiconductor integrated circuit characterized in that a complementary MOS high impedance output circuit is composed of an output circuit according to Claim 16, and a semiconductor integrated circuit device provided with a plurality of said complementary MOS high impedance output circuits is connected to a signal transmission line for common use.
References Cited (Backward Citations)
EP0228146A1
Cited
JPH0222917A
Cited
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