EP0517431A1
Expired / Lapsed
EP
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Circuit and method of switching between redundant clocks for a phase lock loop
Assignee: Motorola Solutions Inc
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Filing: 1992-05-28
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Granted: —
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Expires: 2012-05-28
Abstract
Abstract A phase lock loop monitors the frequency of redundant input clock signals (REFCLK₁AND REFCLK₂) and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal (RC_CLK) maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.
Inventors
- 👤 Lanny L. Parker
- 👤 Ahmad H. Atriss
- 👤 Dean William Mueller
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 10:09
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/14; H03L7/143; H03L7/07; H03L7/0807; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
79 words
A method of selecting between redundant first and second input clock signals applied to a phase lock loop (PLL), comprising the steps of: checking the validity of the first input clock signal (54-66) and locking the PLL thereto if valid; switching to the second input clock signal (72) if the first input clock signal becomes invalid; and checking the validity of the second input clock signal (76) and locking the PLL to the second input clock signal if valid.
Claim 2
Dependent Claim
32 words
A method according to claim 1, wherein the step of checking the validity of the first or second input clock comprises comparing the time between transitions of the clock with a threshold.
Claim 3
Dependent Claim
116 words
A phase lock loop (PLL) responsive to a first digital signal for generating a second digital signal operating substantially at frequency and in-phase with said first digital signal, said phase lock loop comprising: first means (12) responsive to first and second control signals for selecting between first and second input clock signals respectively applied at first and second inputs thereof for providing the first digital signal of the PLL at an output; and second means (14) for monitoring the validity of said first and second input clock signals and activating said first control signal when the first input clock signal is valid and activating said second control signal when the first input clock signal is invalid.
Claim 4
Dependent Claim
198 words
A phase lock loop (PLL), comprising: first means (16-18) for comparing the phase of first and second digital input signals and generating an output signal to charge and discharge a loop node; a voltage controlled oscillator (24) having an input coupled for receiving said output signal of said first means and providing a oscillator signal operating at a frequency as determined by said output signal of said first means; second means (30) having an input coupled for receiving said oscillator signal from said voltage controlled oscillator and dividing down the frequency thereof for providing a first divided-down signal which is applied as said second digital input signal to said first means; a first multiplexer circuit (12) responsive to first and second control signals for selecting between first and second input clock signals respectively applied at first and second inputs thereof for providing said first digital input signal to said first means at an output; and third means (14) for monitoring the validity of said first and second input clock signals and activating said first control signal when said first input clock signal is valid and activating said second control signal when said first input clock signal is invalid.
Claim 5
Dependent Claim
63 words
The phase lock loop of claim 4 wherein said third means includes an oscillator circuit (104) for generating an oscillator signal which is applied at a third input of said first multiplexer circuit, said oscillator signal being routed to said output of said first multiplexer circuit in response to a third control signal when said first and second input clock signals are invalid.
Claim 6
Dependent Claim
78 words
The phase lock loop of claim 5 further including: fourth means (32) having an input coupled for receiving said oscillator signal from said voltage controlled oscillator and dividing down the frequency thereof for providing a second divided-down signal; and a second multiplexer circuit (34) responsive to said third control signal for selecting between said first and second divided-down signals respectively applied at first and second inputs thereof for providing said second digital input signal to said first means.
Claim 7
Dependent Claim
190 words
The phase lock loop of claim 6 wherein said third means further includes: a first clock generator (90) having an input coupled for receiving said first input clock signal and having first and second outputs for providing first and second non-overlapping clock signals, said first non-overlapping clock signal operating in-phase with said first input clock signal, said second non-overlapping clock signal operating of complementary phase with said first input clock signal; a first frequency divider circuit (94) having first and second inputs coupled for receiving said first and second non-overlapping clock signals from said first clock generator and providing a first frequency-divided clock signal; a first frequency detector circuit (98) having an input coupled for receiving said first frequency-divided clock signal and providing a first error signal when said first frequency-divided clock signal substantially deviates from a predetermined frequency of operation as determined by said oscillator signal; and a clock selector circuit (112) having a first input coupled for receiving said first error signal and providing said first control signal to said multiplexer circuit when said first frequency-divided clock signal is in the vicinity of said predetermined frequency of operation.
References Cited (Backward Citations)
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