EP0516279A2
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EP
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An interconnection structure of a semiconductor device and a method of manufacturing thereof
Assignee: Mitsubishi Electric Corp
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Filing: 1992-04-24
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Granted: —
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Expires: 2012-04-24
Abstract
Abstract An aluminum interconnection film (49) has a three layered structure of an aluminum alloy film (33), a tungsten film (58), and a titanium nitride film (35). An aluminum interconnection film (61) and an aluminum interconnection film (49) are electrically connected through a through hole (55) formed in a silicon oxide film (51). Because light reflectivity of the titanium nitride film (35) is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step (30) where light is irregularly reflected. Therefore, it is possible to form a through hole (55) of a desired dimension even if the through hole (55) is formed above the step (30). Even if the titanium nitride film (35) is etched and removed in forming the through hole (55), the aluminum alloy film (33) is not exposed since the etching speed of the silicon oxide film (51) is considerably slower than that of the tungsten film (58). The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film (33) does not occur.
Inventors
- 👤 Atsushi c/o Mitsubishi Denki k. k. ISI Ishii
- 👤 Yoshihumi c/o Mitsubishi Denki k. k. ISI Takata
- 👤 Akihiko c/o Mitsubishi Denki k. k. ISI Ohsaki
- 👤 Kazuyoshi c/o Mitsubishi Denki k. k. ISI Maekawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 16:14
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425; Y; Y10; Y10S; Y10S257/00; Y10S257/915
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
162 words
An interconnection structure of a semiconductor device having each of multilayer interconnection layers connected through a connection hole, comprising: a first interconnection layer (49), an insulating layer (51) formed on said first interconnection layer (49) having a through hole (55) reaching the surface of said first interconnection layer (49), and a second interconnection layer (61) formed on said insulating layer (51), electrically connected to said first interconnection layer (49) through said through hole (55), wherein said first interconnection layer (49) comprises a first conductive layer (33) containing metal, a second conductive layer (58) formed on said first conductive layer (33), and a third conductive layer (35) formed on said second conductive layer (58), wherein the etching speed of said second conductive layer (58) is less than that of said third conductive layer (35) under condition of etching said insulating layer (51), and further wherein light reflectivity of said third conductive layer (35) is less than that of said second conductive layer (58).
Claim 2
Dependent Claim
31 words
The interconnection structure of the semiconductor device according to claim 1, wherein said first interconnection layer (49) comprises a step (30) with said through hole (55) located above said step (30).
Claim 3
Dependent Claim
20 words
The interconnection structure of the semiconductor device according to claim 1, wherein said third conductive layer (35) comprises titanium nitride.
Claim 4
Dependent Claim
22 words
The interconnection structure of the semiconductor device according to claim 3, wherein said third conductive layer (35) has a thickness of 300-500Å.
Claim 5
Dependent Claim
34 words
The interconnection structure of said semiconductor device according to claim 1, wherein said second conductive layer (58) comprises at least a material selected from the group consisting of tungsten, tungsten silicide, and molybdenum silicide.
Claim 6
Dependent Claim
35 words
The interconnection structure of the semiconductor device according to claim 5, wherein the thickness of said second conductive layer (58) comprising at least one of said tungsten or said tungsten silicide is 500Å and above.
Claim 7
Dependent Claim
32 words
The interconnection structure of the semiconductor device according to claim 1, wherein the etching speed of said second conductive layer (58) is at most 1/10 of that of said insulating layer (51).
Claim 8
Dependent Claim
24 words
The interconnection structure of the semiconductor device according to claim 7, wherein said second conductive layer (58) has a thickness of 1000Å and below.
Claim 9
Dependent Claim
19 words
The interconnection structure of the semiconductor device according to claim 7, wherein said second conductive layer (58) comprises tungsten.
Claim 10
Dependent Claim
47 words
The interconnection structure of the semiconductor device according to claim 1, wherein said second interconnection layer (73) comprises a main conductive layer (75) which becomes a main portion of said second interconnection layer, and a first titanium nitride containing layer (77) formed on said main conductive layer.
Claim 11
Dependent Claim
60 words
The interconnection structure of the semiconductor device according to claim 10, wherein said second interconnection layer (79) further comprises a second titanium nitride containing layer (87) formed beneath said main conductive layer (83), and a titanium containing layer (85) formed beneath said second titanium nitride containing layer (87), having contact with said second conductive layer (58) through said through hole.
Claim 12
Dependent Claim
35 words
The interconnection structure of the semiconductor device according to claim 10, wherein said first interconnection layer (49) and said second interconnection layer (73) are electrically connected by tungsten (89) formed in said through hole (55).
Claim 13
Dependent Claim
35 words
The interconnection structure of the semiconductor device according to claim 1, wherein said first conductive layer (33) comprises at least a material selected from the group consisting of aluminum alloy containing copper, aluminum, and copper.
Claim 14
Dependent Claim
89 words
The interconnection structure of the semiconductor device according to claim 1, including a plurality of said first interconnection layers (49a, 49b) at first and second depths (55a, 55b) in said insulating layer (71), wherein said second conductive layer (58) of the first interconnection layer (49a) deeper in said insulating layer (71) has a minimum thickness, prior to etching thereof, corresponding to the etching speed of said second conductive layer (58) under condition of etching said insulating layer (71), and the difference between said first and second depths (55a, 55b).
Claim 15
Dependent Claim
23 words
The interconnection structure of the semiconductor device according to claim 14, wherein said minimum thickness of said second conductive layer (58) is 500Å.
Claim 16
Dependent Claim
23 words
The interconnection structure of the semiconductor device according to claim 1, wherein said second conductive layer (58) has a maximum thickness of 1000Å.
Claim 17
Independent Claim
205 words
A method of manufacturing an interconnection structure of a semiconductor device having a first interconnection layer (49) and a second interconnection layer (61) connected by a through hole (55) formed in an insulating layer (51), comprising the steps of: forming a first conductive layer (33) containing metal, a second conductive layer (58), and a third conductive layer (35) in sequence on the main surface of a substrate (27), wherein the etching speed of said second conductive layer (58) is slower than that of said third conductive layer (35) under the etching condition of said insulating layer (51), wherein light reflectivity of said third conductive layer (35) is lower than that of said second conductive layer (58), forming said insulating layer (51) on said first interconnection layer (49) including said first, second, and third conductive layers (33, 58, 35), forming a resist (53) on said insulating layer (51), patterning said resist (53) to a predetermined configuration using photolithography, selectively etching said insulating layer (51) using said resist (53) as a mask to form said through hole (55), forming said second interconnection layer (61) on said insulating layer (51) to connect said first interconnection layer (49) and said second interconnection layer (61) through said through hole (55).
Claim 18
Dependent Claim
39 words
The method of manufacturing the interconnection structure of the semiconductor device according to claim 17, further comprising the step of filling tungsten into said through hole (55) using selective CVD method after the formation of said through hole (55).
Claim 19
Dependent Claim
26 words
The method of manufacturing the interconnection structure of the semiconductor device according to claim 17, wherein said through hole (55) is located above a step (30).
References Cited (Backward Citations)
No citation records indexed.
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