EP0512536A2
Expired / Lapsed
EP
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Programmable logic unit circuit and programmable logic circuit
Assignee: Toshiba Corp
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Filing: 1992-05-07
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Granted: —
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Expires: 2012-05-07
Abstract
Abstract A programmable logic unit circuit comprising a data memory circuit (10), a combinational logic circuit (13) supplied with at least two input signals, two input select circuits (11,12) for, based on the stored data in the data memory circuit (10), selecting the two input signals supplied to the combinational logic circuit (13) from more than two input signals, a clock-synchronized circuit (14) for supplying the output signal from the combinational logic circuit (13) in synchronization with a clock signal, and a 3-state-output type output select circuit (16) for selecting either the output signal of the combinational logic circuit (13) or the output signal of the clock-synchronized circuit (14), depending on the stored data in the data memory circuit (10).
Inventors
- 👤 Yukihiro C/O Intellectual Property Div. Saeki
- 👤 Hiroki c/o Intellectual Property Div. Muroga
- 👤 Tomohisa C/O Intellectual Property Div Shigematsu
- 👤 Toshio c/o Intellectual Property Div. Hibi
- 👤 Yasuo c/o Intellectual Property Div. Kawahara
- 👤 Kazunao c/o Intellectual Property Div. Maru
- 👤 Kenneth Austin
- 👤 Gordon Stirling Work
- 👤 Darren Martin Wedgwood
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 07:26
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17764; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/41; G11C11/412; H03K19/17704; H03K19/17724; H03K19/17728; H03K19/17736; H03K19/1774
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
138 words
A programmable logic unit circuit characterized by comprising: a combinational logic circuit (13) which is supplied with at least two input signals (A, B) and produces a particular logic output signal from those input signals; at least two input select circuits (11, 12) for, based on first selecting data, selecting at least two input signals supplied to said combinational logic circuit from more than two input signals; a clock-synchronized circuit (14) which latches the output signal from said combinational logic circuit and outputs it upon receipt of a clock signal; a 3-state-output type output select circuit (16) for selectively supplying either the output signal of said combinational logic circuit or the output signal of said clock-synchronized circuit, depending on second selecting data; and a data memory circuit (10) for storing at least said first and second selecting data.
Claim 2
Dependent Claim
150 words
A programmable logic unit circuit characterized by comprising: a combinational logic circuit (13) which is supplied with at least two input signals (A, B) and produces a particular logic output signal from those input signals; at least two input select circuits (11, 12) for, based on first selecting data, selecting at least two input signals supplied to said combinational logic circuit from more than two input signals; a clock-synchronized circuit (14) which latches the output signal from said combinational logic circuit and outputs it upon receipt of a clock signal, and which resets the latched contents in response to a reset signal; a 3-state-output type output select circuit (16) for selectively supplying either the output signal of said combinational logic circuit or the output signal of said clock-synchronized circuit, depending on second selecting data; and a data memory circuit (10) for storing at least said first and second selecting data.
Claim 3
Dependent Claim
45 words
A programmable logic unit circuit according to claim 1 or 2, characterized in that said combinational logic circuit (13) allows the logical state of the output signal for said input signals to be changed according to third data stored in said data memory circuit (10).
Claim 4
Dependent Claim
23 words
A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 1 or 2 arranged in matrix form.
Claim 5
Dependent Claim
39 words
A programmable logic unit circuit according to claim 1 or 2, characterized in that each of said input select circuits (11, 12) selects a signal, based on first data of complementary levels stored in said data memory circuit (10).
Claim 6
Dependent Claim
43 words
A programmable logic unit circuit according to claim 1 or 2, characterized in that one of said at least two input select circuits (11, 12) supplies at least one of its output signal as an input signal to the other input select circuit.
Claim 7
Dependent Claim
40 words
A programmable logic unit circuit according to claim 1 or 2, characterized in that said at least two input select circuits (11, 12) are each supplied with a fixed value logic signal as one of two or more input signals.
Claim 8
Dependent Claim
44 words
A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 1, at least one of which has said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as said clock signal.
Claim 9
Dependent Claim
44 words
A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 2, at least one of which has said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as said reset signal.
Claim 10
Dependent Claim
50 words
A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 1 or 2, at least one of which has said output select circuit (16) supplied with one of the input signals to said combinational logic circuit (13) as a control signal for 3-state control.
Claim 11
Dependent Claim
71 words
A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 1, at least one of which has said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as said clock signal, and has said output select circuit (16) supplied with one of the input signals to said combinational logic circuit (13) as a control signal for 3-state control.
Claim 12
Dependent Claim
71 words
A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 2, at least one of which has said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as said reset signal, and has said output select circuit (16) supplied with one of the input signals to said combinational logic circuit (13) as a control signal for 3-state control.
Claim 13
Dependent Claim
99 words
A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 1, a first one of which has said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as said clock signal; and a second one of which has said output select circuit (16) supplied with one of the input signals to said combinational logic circuit (13) as a control signal for output selection, and has said clock-synchronized circuit (14) supplied with the clock signal used in said first programmable logic unit circuit as a clock signal.
Claim 14
Dependent Claim
161 words
A programmable logic circuit characterized by comprising: a plurality of programmable logic unit circuits of claim 2, a first one of which has said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as said clock signal; a second one of which has said output select circuit (16) supplied with one of the input signals to said combinational logic circuit (13) as a control signal for output selection, and has said clock-synchronized circuit (14) supplied with the clock signal used in said first programmable logic unit circuit as a clock signal; said second programmable logic unit circuit also having said clock-synchronized circuit (14) supplied with one of the input signals to said combinational logic circuit (13) as a reset signal; and said first programmable logic unit circuit also having its clock-synchronized circuit (14) supplied with the reset signal to the clock-synchronized circuit (14) of said second programmable logic unit circuit, as a reset signal.
Claim 15
Dependent Claim
36 words
A programmable logic circuit according to claim 13 or 14, characterized in that the clock signals supplied to the clock-synchronized circuits (14) of said first and second programmable logic units, respectively, are complementary to each other.
Claim 16
Dependent Claim
31 words
A programmable logic circuit according to claim 15, characterized in that said first and second programmable unit circuits are formed in the same integrated circuit so as to adjoin each other.
Claim 17
Dependent Claim
102 words
A programmable logic unit circuit characterized by comprising: a memory circuit (10) for storing data; a logic circuit (13) whose circuit function is changed according to the stored data in said memory circuit; read control means (WL1, WL2, WL1-1 to WL1-4, WL2-1 to WL2-3, WL3-1 to WL3-4) for controlling the reading of data from said memory circuit; data lines (BL6, BL7) for transferring the data read from said memory circuit; and observation control means (61, WL1, WL3) which contains part of said read control means and which controls the reading of the signal at any node in said logic circuit for observation.
Claim 18
Dependent Claim
29 words
A programmable logic unit circuit according to claim 17, characterized in that the signal read from a given node in said logic circuit is transferred via said data lines.
Claim 19
Dependent Claim
29 words
A programmable logic unit circuit according to claim 18, characterized in that a pair of signals of complementary levels are read from a given node in said logic circuit.
Claim 20
Dependent Claim
28 words
A programmable logic unit circuit according to claim 17, characterized in that said read control means contains a memory circuit select line (WL1) connected to said memory circuit.
Claim 21
Dependent Claim
66 words
A programmable logic unit circuit according to claim 20, characterized in that said observation control means contains: signal lines (BL6, BL7) for transferring the signal read from a given node in said logic circuit; and switch means (61) which is inserted between a given node in said logic circuit and said signal lines, and which is controlled by the signal on said memory circuit select line.
Claim 22
Dependent Claim
47 words
A programmable logic unit circuit according to claim 17, characterized in that said observation control means is inserted between a given node in said logic circuit and said data lines, and is controlled by a separate signal different from the signal on said memory circuit select line.
References Cited (Backward Citations)
No citation records indexed.
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