Image coding apparatus

Claim 2

An apparatus according to claim 1, further having reading operation delay means for delaying said frame change request and transferring to said read address generator (31) when said write address at a time point when the frame change request is generated is located within a predetermined range from the head.

Claim 3

An image coding apparatus in which an input image signal that is supplied at a predetermined frame rate in accordance with the order of image scanning lines whose horizontal scan has a priority to the vertical scan is sequentially coded at a rate independent to said frame rate, thereby obtaining a coded image signal for transmission whose frames are thinned out, comprising: a frame memory (110, 204) which has a memory area corresponding to one frame of the input image signal that is specified by horizontal and vertical two-dimensional addresses and which is used to store said input image signal; a write address generator (32) to sequentially generate write addresses in said frame memory in accordance with the order of the image scanning lines of the input image signal; coding means (6, 6a) for executing a coding process by using the signal which is read out from the frame memory; a read address generator (31) to sequentially generate read addresses in the frame memory in response to a frame change request which is generated from said coding means; and write limiting means (50, 51, 58) for comparing said write address and said read address, for stopping the subsequent writing operation of the frames written in the frame memory when the write address approaches the read address, and for restarting the writing operation from the head of the next frame.

Claim 4

An apparatus according to claim 3, wherein said write limiting means compares a vertical address of said write address and a vertical address of said read address.

Claim 5

An apparatus according to claim 3, wherein said write limiting means compares a value which is obtained by converting said write address into a one-dimensional address and a value which is obtained by converting said read address into a one-dimensional address.

Claim 6

An apparatus according to claim 3, further having reading operation delay means for delaying said frame change request and for transferring to said read address generator when said write address at a time point when the frame change request is generated is located within a predetermined range from the head.

Claim 7

An apparatus according to claim 6, wherein said reading operation delay means delays said frame change request when a vertical address of said write address is located within a predetermined range from the head.

Claim 8

An image coding apparatus for sequentially coding an input image signal which is supplied at a predetermined frame rate by a rate independent of said frame rate, thereby obtaining a coding image signal for transmission from which frames are thinned out, comprising: first and second frame memories (4a, 4b) each having a recording area corresponding to one frame of the input image signal for storing the input image signal; coding means (6a) for executing a coding process by using both of the input image signal which is read out from one of said first and second frame memories and a reference signal which is read out from the other one of the first and second frame memories; decoding means (83) for decoding a coding image signal which is generated from said coding means; signal path change means (100, 101) for allowing said first and second frame memories to alternately execute a first operation for reading out the stored input image signal and supplying to said coding means and writing the decoding image signal which is generated from said decoding means and a second operation for reading out the stored decoding image signal as a reference signal and supplying to said coding means and writing the input image signal in response to the frame change request which is generated from said coding means; and write limiting means provided for each of said first and second frame memories, for stopping the subsequent writing operation of the frames written when the write address of the input image signal in said second operation approaches the read address of the reference signal and for restarting the writing operation from the head of the next frame.