EP0510607A1
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Canon Inc
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Filing: 1992-04-22
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Granted: —
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Expires: 2012-04-22
Abstract
Abstract A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate electrode provided on the channel region with a gate insulator therebetween, the gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of the main electrode regions.
Inventors
- 👤 Mamoru C/O Canon Kabushiki Kaisha Miyawaki
- 👤 Akira C/O Canon Kabushiki Kaisha Ishizaki
- 👤 Genzo c/o Canon Kabushiki Kaisha Monma
- 👤 Hiroshi C/O Canon Kabushiki Kaisha Yuzurihara
- 👤 Tetsunobu C/O Canon Kabushiki Kaisha Kohchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 04:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/62; H10D30/6211; H10B; H10B12/00; H10B12/30; H10B69/00; H10D30/01; H10D30/021; H10D30/024; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0149; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
73 words
A semiconductor memory device comprising: an insulated gate transistor including a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between said plurality of main electrode regions, and a gate electrode provided on said channel region with a gate insulator therebetween, said gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of said main electrode regions.
Claim 2
Dependent Claim
34 words
A semiconductor memory device according to claim 1, wherein said memory element has a semiconductor layer, and wherein writing is performed by breaking a junction between said semiconductor layer and another layer adjoining thereto.
Claim 3
Dependent Claim
46 words
A semiconductor memory device according to claim 1, wherein said gate electrode and a high impurity concentration semiconductor region provided adjacent to said channel region in combination enclose at least four surfaces of said channel region which run in a direction in which carriers are mobilized.
Claim 4
Dependent Claim
53 words
A semiconductor memory device according to claim 3, further comprising a second semiconductor region provided on the surface of said channel region which is remote from said high impurity concentration semiconductor region and having the same conductivity type as that of said channel region and a higher impurity concentration than said channel region.
Claim 5
Dependent Claim
50 words
A semiconductor memory device according to claim 1, further comprising a third semiconductor region provided between said main electrode regions and said channel region, said third semiconductor region having the same conductivity type as that of said main electrode regions and a lower impurity concentration than said main electrode regions.
Claim 6
Dependent Claim
29 words
A semiconductor memory device according to claim 1, further comprising an interconnection for a power source which runs in a direction of the source and drain of said transistor.
Claim 7
Dependent Claim
32 words
A semiconductor memory device according to claim 1, wherein an interconnection for a power source is disposed in a direction which crosses a direction of the source and drain of said transistor.
Claim 8
Dependent Claim
131 words
A semiconductor memory device comprising: a plurality of memory cells each of which includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between said plurality of main electrode regions, and a gate electrode provided on said channel region with a gate insulator therebetween, said gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of said main electrode regions, wherein said plurality of memory cells are matrix connected by a first interconnection which is common to the gate electrodes of said memory cells and a second interconnection which is common to the memory elements of said memory cells, a power source line being disposed between said second interconnections.
Claim 9
Dependent Claim
100 words
A semiconductor memory device comprising: an insulated gate type transistor including a plurality of main electrode regions and a channel region provided between said plurality of main electrode regions, a gate electrode provided on said channel region with a gate insulator provided therebetween, and a semiconductor region -provided in contact with said channel region, said semiconductor region having the same conductivity type as that of said channel region and a higher impurity concentration than said channel region, said gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of said main electrode regions.
Claim 10
Dependent Claim
83 words
A semiconductor memory device according to claim 9, wherein a plurality of memory cells, including said transistor and said memory element, are provided, said plurality of memory cells being matrix connected to each other by a plurality of first interconnections which are common to the gate electrodes of said plurality of memory cells, and a plurality of second interconnections which are common to the memory elements of said plurality of memory cells, a power source line being disposed between the adjacent second interconnections.
References Cited (Backward Citations)
EP0253631A2
Cited
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