EP0510241A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Upgradeable/downgradeable computer
Assignee: Acer Inc
•
Filing: 1991-06-19
•
Granted: —
•
Expires: 2011-06-19
Abstract
Abstract A computer system is made capable of accepting more than one type of central processor including a plurality of sockets for receiving more than one type of identification signal, a clock generator responsive to said identifying signal for generating clock signals for the identified type of processor, and means responsive to said identifying signal for disabling and enabling signal paths from the socket. <IMAGE>
Inventors
- 👤 Te-Chih Chuang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 06:44
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F9/3879; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
88 words
A computer system upgradeable/downgradeable by more than one model of processor, the computer system comprises a circuit board, the circuit board comprises: a first socket for receiving a first processor; an identifying circuit for generating an signal identifying the model of said first processor in the first socket; a clock generator responsive to said identifying signal for generating clock frequency for the processor in the first socket; and an enabling circuit responsive to the identifying signal for enabling and disabling signals to the processor in the first socket.
Claim 2
Dependent Claim
21 words
The computer system of claim 1, wherein the identifying comprises means for detecting signal state of an output of the socket.
Claim 3
Dependent Claim
28 words
The computer system of claim 1 or 2, wherein the enabling circuit comprises at least two tri-level gates for selectively passing signals in response to the identifying signal.
Claim 4
Dependent Claim
20 words
The computer system of one of claims 1 to 3, further comprising a second socket for receiving a second processor.
Claim 5
Dependent Claim
24 words
The computer system of claim 4, comprising means responsive to a signal from the processor in the first socket for disable the second processor.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.