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EP0509722A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Data transfer system

Assignee: NEC Corp
•
Filing: 1992-04-10
•
Granted: —
•
Expires: 2012-04-10
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Abstract

Abstract A data transfer system includes a buffer (28) having a plurality of buffer areas for storing the data blocks transferred from plural central processors (10,12,14,16), and an external pointer (32) storing an address data corresponding to an initial position of one of the buffer areas where a transferring data block is to be stored therein. The address data stored in the external pointer (32) is updated in accordance with the length (Lb) of a data block to be transferred. The length data (Lb) is supplied with the address to the external pointer (32) where the length data (Lb) is added (50) to the buffer area address (PTRe) output by a RAM (46) and the sum (X) is stored as the next buffer area address (PTRe) in the RAM (46). <IMAGE>

Inventors

  • 👤 Hideto Suzuki

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-27 09:39
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F2205/00; G06F2205/10; G06F2205/108

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 88 words
A data transfer system, comprising: at least two processors each having a predetermined data block to be transferred; a buffer having a predetermined number of buffer areas for storing data blocks transferred from said at least two processors; and an external pointer storing an address data designating to an initial position of one of said buffer areas; wherein said address data is increased or decreased by a value determined in accordance with a ratio between a length of said data block and a length of said buffer areas.
Claim 2
Dependent Claim 84 words
A data transfer system, according to claim 1, further comprising: an internal pointer storing an address data designating an initial position of said buffer areas storing said data block transferred from said processors, wherein said data block has a header representing said initial position of said data block; and said header is searched when said data block stored in said buffer is read; and said stored data block is read from said header in accordance with said address data stored in said internal pointer.
Claim 3
Dependent Claim 36 words
A data transfer system, according to claim 2, wherein: said address data is corrected to be an address data representing a position of said searched header, if said header is not set at a predetermined position.
Claim 4
Dependent Claim 150 words
A data transfer system, comprising: a plurality of central processors each controlling a transfer of a data block; a buffer memory for storing data blocks transferred through a system bus from said plurality of central processors; a bus arbitration circuit for arbitrating a use of said system bus by a central processor selected from said plurality of central processors; and a pointer for storing an address signal designating an initial address of said buffer memory; wherein said central processor selected from said plurality of central processors accesses to said pointer to read said address signal, and provides an increment data determined by a length of a transfer data block and a length of a storing area of said buffer memory; said address signal of said pointer is increased by said increment data; and said transfer data is transferred from said central processor to said initial address of said buffer memory.
Claim 5
Dependent Claim 57 words
A data transfer system, according to claim 4, wherein: said pointer is included in an I/O panel, said I/O panel including a further pointer for storing an address signal designating an initial address of said buffer memory, a data block being read from said initial address; of said buffer memory to be transferred to a periphery circuit.
Claim 6
Dependent Claim 29 words
A data transfer system, according to claim 5, wherein: said pointer is accessed by said plurality of central processors, while said further pointer is accessed by said I/O panel.

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