Telephone communication system having an enhanced timing circuit

Claim 2

A circuit comprising: signal synthesizing means, responsive to an input signal, for generating a first plurality of frequency synthesized output signals, each one of said first plurality of output signals having a different frequency; and phase-locked loop circuit means, coupled to the signal synthesizing means, for providing at an output of such phase-locked loop circuit means, a control signal indicating the deviation of the frequency of at.least one of the plurality of frequency synthesized output signals from a reference frequency.

Claim 3

The circuit recited in Claim 1 further comprising first selector means, fed by said at least one of the plurality of frequency synthesized output signals and said input signal, for coupling either one of the signals fed to the first selector means to the phase-locked loop circuit means selectively in response to a control signal.

Claim 4

The circuit recited in Claim 2 further comprising means, coupled to the phase-locked loop circuit means, for generating a second plurality of frequency synthesized output signals, the frequencies of said second plurality of frequency synthesized output signals corresponding to the frequencies of said first plurality of frequency synthesized output signals.

Claim 5

The circuit recited in Claim 3 further comprising an output selector means, coupled to the first plurality of frequency synthesized output signals and to the second plurality of frequency synthesized output signals, for coupling, in response to a control signal, either said first plurality of output signals or said second plurality of output signals to a plurality of outputs of said output selector means.

Claim 6

The circuit recited in Claim 2 wherein the signal synthesizing means includes second selector means, fed by said input signal and an alternate input signal, for coupling either the input signal or the alternate input signal to an output thereof selectively in response to a control signal and wherein said signal synthesizing means generates said first plurality of frequency synthesized output signals in response to the selected one of either the input signal or the alternate input signal.

Claim 7

A signal synthesizing and frequency monitoring circuit comprising: signal synthesizing means fed by an input signal for generating, in response to said input signal, a first plurality of frequency synthesized output signals, each one of said first plurality of output signals having a different frequency, such frequency being an integer multiple of the frequency of the input signal; and phase-locked loop circuit means comprising a phase comparatorfed by at least one of said first plurality of frequency synthesized output signals and a voltage control oscillator coupled to said phase comparator, said voltage controlled oscillator having a center frequency associated therewith and said phase-locked loop circuit means having a bandwidth frequency range associated therewith, for providing a logic signal in a first state when the deviation caused by the frequency of the one of the plurality of frequency synthesized output signals fed thereto from said center frequency is within said bandwidth frequency range and in a second state when the deviation caused by the frequency of the one of the plurality of frequency synthesized output signals fed thereto from said center frequency is outside of said bandwidth frequency range.

Claim 8

A signal synthesizing and frequency monitoring circuit comprising: signal synthesizing means fed by an input signal for generating, in response to said input signal, a first plurality of frequency synthesized output signals, each one of said first plurality of output signals having a different frequency, such frequency being an integer multiple of the frequency of the input signal; and phase-locked loop circuit means comprising a phase comparatorfed by at least one of said first plurality of frequency synthesized output signals and a voltage control oscillator coupled to said phase comparator, said voltage controlled oscillator having a center frequency associated therewith and said phase-locked loop circuit means having a bandwidth frequency range associated therewith, for providing a logic signal in a first state when the deviation caused by the frequency of the one of the plurality of frequency synthesized output signals fed thereto from said center frequency is within said bandwidth frequency range and in a second state when the deviation caused by the frequency of the one of the plurality of frequency synthesized output signals fed thereto from said center frequency is outside of said bandwidth frequency range.

Claim 9

A signal synthesizing and monitoring circuit comprising: (a) primary signal synthesizing circuit comprising: (i) primary selector means, fed by a primary clock signal and a secondary clock signal, for selecting, in response to a primary control signal, either the primary clock signal or the secondary clock signal in response to the primary control signal; and (ii) means, responsive to the selected one of either the primary clock signal or the secondary clock signal, for generating a plurality of primary frequency synthesized output signals, each one of said plurality of output signals having a different frequency; (b) secondary signal synthesizing and monitoring circuit comprising: (i) secondary selector means, fed by said primary clock signal and at least one of said plurality of primary frequency synthesized output signals, for selecting in response to a secondary control signal, either said primary clock signal or said at least one primary frequency synthesized output signal in response to the secondary control signal; and (ii) a phase-locked loop circuit, responsive to the selected one of either the primary clock signal or the at least one frequency synthesized output signal, for generating a plurality of secondary frequency synthesized output signals, each one of said plurality of secondary output signals having a corresponding one of said frequencies, and for producing a selector control signal in accordance with the presence or absence of an error in the frequency of the primary clock signal and/or the at least one of the plurality of primary frequency synthesized output signals; (c) output selector means, fed by said plurality of primary frequency synthesized output signals and said plurality of secondary frequency synthesized output signals, for coupling, in response to an output control signal, either of said pluralities of output signals to a plurality of outputs thereof; and (d) control means, responsive to said selector control signal, for generating said primary control signal, said secondary control signal, and said output control signal.

Claim 10

A signal synthesizing and monitoring circuit comprising: (a) primary signal synthesizing circuit comprising: (i) primary selector means, fed by a primary clock signal and a secondary clock signal, for selecting, in response to a primary control signal, either the primary clock signal or the secondary clock signal in response to the primary control signal; and (ii) means, responsive to the selected one of either the primary clock signal or the secondary clock signal, for generating a plurality of primary frequency synthesized output signals, each one of said plurality of output signals having a different frequency; (b) secondary signal synthesizing and monitoring circuit comprising: (i) secondary selector means, fed by said primary clock signal and at least one of said plurality of primary frequency synthesized output signals, for selecting in response to a secondary control signal, either said primary clock signal or said at least one primary frequency synthesized output signal in response to the secondary control signal; and (ii) a phase-locked loop circuit, responsive to the selected one of either the primary clock signal or the at least one frequency synthesized output signal, for generating a plurality of secondary frequency synthesized output signals, each one of said plurality of secondary output signals having a corresponding one of said frequencies, and for producing a selector control signal in accordance with the presence or absence of an error in the frequency of the primary clock signal and/or the at least one of the plurality of primary frequency synthesized output signals; (c) output selector means, fed by said plurality of primary frequency synthesized output signals and said plurality of secondary frequency synthesized output signals, for coupling, in response to an output control signal, either of said pluralities of output signals to a plurality of outputs thereof; and (d) control means, responsive to said selector control signal, for generating said primary control signal, said secondary control signal, and said output control signal.

Claim 11

A digital loop carrier system coupled between a plurality of subscribers and central office equipment, said digital loop carrier system comprising: a plurality of line cards, each one of said cards corresponding to at least one of the plurality of subscribers and adapted for being coupled thereto; a multiplexer/demultiplexer switch coupled to said plurality of line cards; a plurality of transmission formatting/de-formatting circuits coupled to said multiplexer/demultiplexer switch and adapted for coupling to said central office equipment; and a control circuit and a timing circuit, each of said control and timing circuits being coupled to said plurality of line cards, said multiplexer/demultiplexer switch, and said plurality of transmission formatting/de-formatting circuits, wherein said timing circuit comprises signal synthesizing means, responsive to an input signal, for generating a first plurality of frequency synthesized output signals, each one of said first plurality of output signals having a different frequency; and, phase-locked loop circuit means, coupled to the signal synthesizing means, for providing at an output of such phase-locked loop circuit means, a control signal indicating the deviation-of the frequency of the one of at least plurality of frequency synthesized output signals from a reference frequency.

Claim 12

A digital loop carrier system coupled between a plurality of subscribers and central office equipment, said digital loop carrier system comprising: a plurality of line cards, each one of said cards corresponding to at least one of the plurality of subscribers and adapted for being coupled thereto; a multiplexer/demultiplexer switch coupled to said plurality of line cards; a plurality of transmission formatting/de-formatting circuits coupled to said multiplexer/demultiplexer switch and adapted for coupling to said central office equipment; and a control circuit and a timing circuit, each of said control and timing circuits being coupled to said plurality of line cards, said multiplexer/demultiplexer switch, and said plurality of transmission formatting/de-formatting circuits, wherein said timing circuit comprises signal synthesizing means, responsive to an input signal, for generating a first plurality of frequency synthesized output signals, each one of said first plurality of output signals having a different frequency; and, phase-locked loop circuit means, coupled to the signal synthesizing means, for providing at an output of such phase-locked loop circuit means, a control signal indicating the deviation-of the frequency of the one of at least plurality of frequency synthesized output signals from a reference frequency.

Claim 13

The digital loop carrier system recited in Claim 8 wherein said timing circuit includes a first selector means, fed by said at least one of the plurality of frequency synthesized output signals and said input signal, for coupling either one of the signals fed to the first selector means to the phase-locked loop circuit means selectively in response to a control signal.

Claim 14

The digital loop carrier system recited in Claim 9 wherein said timing circuit includes means, coupled to the phase-locked loop circuit means, for- synthesizing a second plurality of frequency synthesized output signals, the frequencies of said second plurality of frequency synthesized output signals corresponding to the frequencies of said first plurality of frequency synthesized output signals.

Claim 15

The digital loop carrier system recited in Claim 10 wherein said timing circuit further includes an output selector means, coupled to the first plurality of frequency synthesized output signals and to the second plurality of frequency synthesized output signals, for coupling, in response to a control signal, either said first.plurality of output signals or said second plurality of output signals to a plurality of outputs of said output selector means .

Claim 16

The digital loop carrier system recited in Claim 9 wherein the signal synthesizing means includes a second selector means, fed by said input signal and an alternate input signal, for coupling a selected one of either the input signal or the alternate input signal to an output thereof and wherein said signal synthesizing generates said first plurality of frequency synthesized output signals in response to the selected one of either the input signal or the alternate input signal.

Claim 19

The method recited in Claim 13 including the step of coupling, to outputs of the system, the plurality of secondary output signals and providing the primary clocksignal as the second input signal in the absence of an error in the frequency of the primary clock signal and in the presence of an error in the frequency of the selected one of the plurality of primary output signals.

Claim 20

The method recited in Claim 14 including the step of coupling, to outputs of the system, the plurality of primary output signals and providing an alternate clock signal as the first input signal in the presence of.an error in the frequency of the primary clock signal and the absence of an error in the frequency of the selected one of the plurality of primary output signals.

Claim 21

A circuit comprising: selector means, fed by a first signal and a second signal, for selecting said first signal during a first period of time and said second signal during a second period of time; means, responsive to said selected signal, for determining the presence or absence of an error in the frequency of said first signal during said first period of time and the presence or absence of an error in the frequency of said second signal during said second period of time; and signal synthesizing means, responsive to an input signal, for producing, at one of a pair of outputs thereof, said first signal, and wherein said selector means includes means for dividing, during said first time period, the frequency of the first signal by a factor corresponding to the one of the pair of outputs of said signal synthesizing means where said signal is produced.

Claim 22

A circuit comprising: selector means, fed by a first signal and a second signal, for selecting said first signal during a first period of time and said second signal during a second period of time; means, responsive to said selected signal, for determining the presence or absence of an error in the frequency of said first signal during said first period of time and the presence or absence of an error in the frequency of said second signal during said second period of time; and signal synthesizing means, responsive to an input signal, for producing, at one of a pair of outputs thereof, said first signal, and wherein said selector means includes means for dividing, during said first time period, the frequency of the first signal by a factor corresponding to the one of the pair of outputs of said signal synthesizing means where said signal is produced.

Claim 23

The circuit recited in Claim 16 wherein said signal synthesizing means, produces said first signal, in response to said second signal.

Claim 24

The circuit recited in Claim 17 wherein said selector means is fed by a third signal and includes means for selecting said third signal during a third period of time and wherein said third signal is produced at a second output of said signal synthesizing means.