Contactless flash EPROM cell using a standard row decoder

Claim 1

An EPROM cell array formed in a silicon substrate, the EPROM cell array comprising: (a) an N+ source line formed in the silicon substrate; (b) first and second N+ drain lines formed in parallel with and spaced-apart from the source line on opposite sides of the source line; (c) first and second field oxide strips formed in parallel with and spaced-apart from the first and second drain lines, respectively, such that the source line/drain line structure is bordered by the first and second field oxide strips to separate such structure from adjacent similar source/drain line structures in the array; (d) first and second lines of first polysilicon (polysilicon 1) overlying the channel regions between the first drain line and the source line and the second drain line of a source line, respectively, and separated therefrom by a first dielectric material; and (e) a plurality of spaced-apart parallel word lines of second polysilicon (polysilicon 2) overlying and running perpendicular to the first and second polysilicon 1 lines and spaced-apart therefrom by a second dielectric material whereby EPROM cells of the array are defined at each crossing of the polysilicon 1 lines and the polysilicon 2 word lines.

Claim 4

A method of forming an EPROM cell array in the silicon substrate, the method comprising: (a) forming parallel, spaced-apart strips of field oxide in the silicon substrate; (b) forming a layer of first dielectric material on the silicon substrate between the field oxide strips; (c) forming a layer of first polysilicon (polysilicon 1) over the layer of first dielectric material; (d) forming a layer of second dielectric material over a layer of first polysilicon; (e) masking the structure formed in steps (d) and (e) and patterning said structure to define first and second polysilicon 1 lines that are spaced-apart from one another and from the adjacent field oxide strips and are separated from the substrate by the first dielectric material and have second dielectric material formed thereon; (f) simultaneously forming an N+ source line in the substrate between the first and second polysilicon lines and first and second N+ drain lines in the substrate between the first polysilicon 1 line and its adjacent field oxide strip and the second polysilicon 1 line and its adjacent field oxide strip, respectively; (g) performing a differential oxide step to simultaneously form additional dielectric material on the second dielectric material overlying the first and second polysilicon 1 lines and oxide material over the N+ source line and the first and second N+ drain lines; (h) forming a plurality of spaced-apart parallel polysilicon 2 word lines overlying and running perpendicular to the first and second polysilicon 1 lines and spaced-apart therefrom by the second dielectric material and additional dielectric material; and (i) performing a stacked etch step utilizing the polysilicon 2 word lines to define the first and second polysilicon 1 lines as the polysilicon 1 floating gates of the EPROM cells in the array whereby the oxide over the N+ source line and the first and second N+ drain lines protects the N+ lines during the stacked etch step and whereby EPROM cells of the array are defined at each crossing of the polysilicon 2 word lines and the underlying polysilicon 1 floating gates.