EP0509489A1
Expired / Lapsed
EP
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Semiconductor integrated circuit with low-noise output buffers
Assignee: Oki Electric Industry Co Ltd
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Filing: 1992-04-15
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Granted: —
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Expires: 2012-04-15
Abstract
Abstract A semiconductor integrated circuit has output buffers connected in parallel between one or more upper potential lines and one or more lower potential lines. Each output buffer has an output terminal coupled by first and third switching circuits (40,80) to upper potential lines, and by second and fourth switching circuits (50,90) to lower potential lines. In the high output state the first switching circuit (40) is switched on, then the third switching circuit (80) is switched on. In the low output state the second switching circuit (50) is switched on, then the fourth switching circuit (90) is switched on. An upper voltage threshold element (42) switches the first switching circuit (40) off above a first threshold output potential. A lower voltage threshold element (51) switches the second circuit (50) off below a second threshold output potential.
Inventors
- 👤 Satoru c/o Oki Electric Industry Co. Ltd. Tanoi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 23:52
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/6871; H03K17/6872; H03K17/16; H03K17/161; H03K17/165; H03K17/166; H03K17/167
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
209 words
A semiconductor integrated circuit having a first and a second upper potential lines for supplying a certain upper potential, a first and a second lower potential lines for supplying a certain lower potential, and a plurality of output buffers connected in parallel between said upper potential lines and said lower potential lines, each output buffer comprising: an output terminal; a first switching circuit for switchably coupling said output terminal to the first upper potential line; a second switching circuit for switchably coupling said output terminal to the first lower potential line; a third switching circuit for switchably coupling said output terminal to the second upper potential line; a fourth switching circuit for switchably coupling said output terminal to the second lower potential line; and a control circuit coupled to switch said first switching circuit on and said second switching circuit and said fourth switching circuit off, then after a certain delay to switch said third switching circuit on, thereby placing said output terminal in a high output state, and to switch said first switching circuit and said third switching circuit off and said second switching circuit on, then after a certain delay to switch said fourth switching circuit on, thereby placing said output terminal in a low output state.
Claim 2
Dependent Claim
38 words
The circuit of claim 1, further comprising an upper voltage threshold circuit coupled to switch said first switching circuit off when said output terminal exceeds a first threshold potential intermediate between said upper potential and said lower potential.
Claim 3
Dependent Claim
39 words
The circuit of claim 2, further comprising a lower voltage threshold circuit coupled to switch said second switching circuit off when said output terminal falls below a second threshold potential intermediate between said upper potential and said lower potential.
Claim 4
Dependent Claim
25 words
The circuit of claim 2, wherein said upper voltage threshold circuit comprises a first field-effect transistor having a gate electrode coupled to said output terminal.
Claim 5
Dependent Claim
35 words
The circuit of claim 4, wherein said first switching circuit comprises a second field-effect transistor coupled in series with said first field-effect transistor between said output terminal and said one of said upper potential lines.
Claim 6
Dependent Claim
21 words
The circuit of claim 5, wherein said first field-effect transistor is coupled between said second field-effect transistor and said output terminal.
Claim 7
Dependent Claim
21 words
The circuit of claim 5, wherein said second field-effect transistor is coupled between said first field-effect transistor and said output terminal.
Claim 8
Dependent Claim
79 words
The circuit of claim 2, wherein: said upper voltage threshold circuit comprises a bipolar transistor having an emitter electrode coupled to said output terminal, a collector electrode coupled to said one of said upper potential lines, and a base electrode; and said first switching circuit comprises a pair of switching elements for coupling said base electrode to said output terminal in said low output state, and to another one of said upper potential lines in said high output state.
Claim 9
Dependent Claim
12 words
The circuit of claim 8, wherein said switching elements are field-effect transistors.
Claim 10
Dependent Claim
25 words
The circuit of claim 3, wherein said lower voltage threshold circuit comprises a third field-effect transistor having a gate electrode coupled to said output terminal.
Claim 11
Dependent Claim
35 words
The circuit of claim 10, wherein said first switching circuit comprises a fourth field-effect transistor coupled in series with said third field-effect transistor between said output terminal and said one of said lower potential lines.
Claim 12
Dependent Claim
22 words
The circuit of claim 11, wherein said third field-effect transistor is coupled between said fourth field effect transistor and said output terminal.
Claim 13
Dependent Claim
21 words
The circuit of claim 11, wherein said fourth field-effect transistor is coupled between said third field-effect transistor and said output terminal.
Claim 14
Dependent Claim
279 words
A buffer circuit comprising: a first high potential line supplying a first high potential signal; a second high potential line supplying a second high potential signal; a first low potential line supplying a first low potential signal; a second low potential line supplying a second low potential signal; an input terminal for receiving an input signal; an output terminal; a control circuit connected to said input terminal for generating a control signal in response to the input signal; a first output circuit connected between said control circuit and said output terminal for outputting a first output signal in response to the control signal, said first output circuit including, a first high potential supplying circuit connected between said first high potential line and said output terminal for outputting a signal having a potential lower than that of the first high potential signal, and a first low potential supplying circuit connected between said first low potential line and said output terminal for outputting a signal having a potential higher than that of the first low potential signal; a delay circuit connected to said control circuit and said output terminal for generating a delay signal in response to the control signal and the first output signal; and a second output circuit connected to said delay circuit for outputting a second output signal in response to the delay signal, said second output circuit including, a second high potential supplying circuit connected between said second high potential line and said output terminal for outputting the second high potential signal, and a second low potential supplying circuit connected between said second low potential line and said output terminal for outputting the second low potential signal.
Claim 15
Dependent Claim
48 words
A buffer circuit of claim 14, wherein the first high potential supplying circuit has a high voltage threshold circuit electrically connected between said first high potential line and said output terminal for electrically disconnecting between them when the potential on said output terminal exceeds a high threshold voltage.
Claim 16
Dependent Claim
28 words
A buffer circuit of claim 15, wherein the high threshold voltage is intermediate between the potentials of the first high potential signal and the first low potential signal.
Claim 17
Dependent Claim
49 words
A buffer circuit of claim 14, wherein the first low potential supplying circuit has a low voltage threshold circuit electrically connected between said first low potential line and said output terminal for electrically disconnecting between them when the potential on said output terminal falls below a low threshold voltage.
Claim 18
Dependent Claim
28 words
A buffer circuit of claim 17, wherein the low threshold voltage is intermediate between the potentials of the first high potential signal and the first low potential signal.
References Cited (Backward Citations)
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