Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
262 words
A monolithic PIN diode switch circuit comprising: a. first and second input ports; b. first and second output ports; c. a first pair of back-to-back monolithic GaAs PIN diodes connected between said first input and said first output ports, said first pair of back-to-back monolithic GaAs PIN diodes having a first bias node between said first pair of back-to-back monolithic GaAs PIN diodes; d. a second pair of back-to-back monolithic GaAs PIN diodes connected between said first input and said second output ports, said second pair of back-to-back monolithic GaAs PIN diodes having a second bias node between said second pair of back-to-back monolithic GaAs PIN diodes; e. a third pair of back-to-back monolithic GaAs PIN diodes connected between said second input and said first output ports, said third pair of back-to-back monolithic GaAs PIN diodes having a third bias node between said third pair of back-to-back monolithic GaAs PIN diodes; and f. a fourth pair of back-to-back monolithic GaAs PIN diodes connected between said second input and said second output ports, said fourth pair of back-to-back monolithic GaAs PIN diodes having a fourth bias node between said fourth pair of back-to-back monolithic GaAs PIN diodes; said first and fourth pairs of monolithic GaAs PIN diodes being connected cathode-to-cathode and said second and third pairs of monolithic GaAs PIN diodes being connected anode-to-anode; said first, second, third and fourth bias nodes being connected to receive a first common bias signal; and said first and second input ports and first and second output ports being connected to receive a second common bias signal.
Claim 2
Dependent Claim
22 words
The circuit of claim 1, wherein said back-to-back PIN diode pairs are directly connected between said input ports and said output ports.
Claim 3
Dependent Claim
17 words
The circuit of claim 1, wherein said circuit is no greater than one square millimeter in area.
Claim 4
Dependent Claim
20 words
The circuit of claim 1, wherein said circuit has only two input ports, two output ports, and eight PIN diodes.
Claim 5
Dependent Claim
13 words
The circuit of claim 1, wherein said PIN diodes are fabricated from GaAs.
Claim 6
Dependent Claim
26 words
The circuit of claim 1, wherein external bias circuitry is connected through RF decoupling circuits to said input ports, said output ports and said bias nodes.
Claim 7
Dependent Claim
15 words
The circuit of claim 6, wherein λ/4 chokes are a portion of said bias circuitry.
Claim 8
Dependent Claim
14 words
The circuit of claim 1, wherein said PIN diodes are in a square configuration.
Claim 9
Dependent Claim
33 words
The circuit of claim 1, wherein said first input port is a transmit port and said second input port is a receive port and said first and second output ports are antenna ports.
Claim 10
Dependent Claim
260 words
A PIN diode switch circuit comprising: first and second input ports; first and second output ports; a first pair of back-to-back semiconductor PIN diodes connected between said first input and said first output ports, said first pair of back-to-back semiconductor PIN diodes having a first bias node between said first pair of back-to-back semiconductor PIN diodes; a second pair of back-to-back semiconductor PIN diodes connected between said first input and said second output ports, said second pair of back-to-back semiconductor PIN diodes having a second bias node between said second pair of back-to-back semiconductor PIN diodes; a third pair of back-to-back semiconductor PIN diodes connected between said second input and said first output ports, said third pair of back-to-back semiconductor PIN diodes having a third bias node between said third pair of back-to-back semiconductor PIN diodes; and a fourth pair of back-to-back semiconductor PIN diodes connected between said second input and said second output ports, said fourth pair of back-to-back semiconductor PIN diodes having a fourth bias node between said fourth pair of back-to-back semiconductor PIN diodes; said first and fourth pairs of semiconductor PIN diodes being connected in one of a cathode-to-cathode arrangement and an anode-to-anode arrangement and said second and third pairs of semiconductor PIN diodes being connected in the other of a cathode-to-cathode arrangement and an anode-to-anode arrangement; said first, second, third and fourth bias nodes being connected to receive a first common bias signal; and said first and second input ports and first and second output ports being connected to receive a second common bias signal.