Instruction buffering device

Claim 2

An instruction buffer device as set forth in claim 1, wherein said bus is divided into a field for the basic segment and a field for said expanded segment.

Claim 3

An instruction buffer device as set forth in claim 2, wherein said control circuit controls, upon outputting said instruction code string to said instruction decoder means, in such a manner that said basic segment of said instruction code sting is output to said field for the basic segment in said bus aligning the most significant bit in order in a tightly packed fashion and said expanded segment of said instruction code string is output to align the least significant bit with the least significant bit in the field for the expanded segment.

Claim 4

An instruction buffer device as set forth in claim 2, wherein, upon outputting N sets of basic segments and said expanded segments of said instruction code string to said bus, said control circuit divides said bus into N fields for the basic segments and N fields for the expanded segments, and is responsive to information that indicates the order of the corresponding basic segment relative to the first basic segment with respect to the expanded segment, to output the relevant expanded segment to a predetermined field position in said fields for said expanded segment.

Claim 5

An instruction buffer device as set forth in claim 2, wherein said bus includes N fields for said basic segments and M fields for said expanded segments corresponding to the basic section constituted of N instruction code strings and an expanded segment constituted of M instruction code strings that is less than or equal to N; and said control circuit performs a control to determine the output position in said fields for said expanded segment depending upon information indicative of the order of the relevant expanded segment in overall expanded segments upon outputting the instruction code in said expanded segment.

Claim 6

An instruction buffer device as set forth in claim 1, wherein said marking providing means provides a marking for a relevant basic segment with information indicative that the basic segment is to be decoded simultaneously with the preceding basis segment.

Claim 7

An instruction buffer device for processing an instruction code string that includes a basic segment including a code for distinguishing the type of instructions and an expanded segment added the depending upon designation of the basic segment; said basic segment and said expanded segment respectively having lengths a multiple of a predetermined unit length; the length of said expanded segment being variable, and one or more said basic segments and said expended segments being combined to form one instruction; said instruction buffer device comprising: instruction buffer means reading out and storing said instruction code sting, a plurality of instruction decoders for simultaneously decoding a plurality of instructions and a plurality of buses connecting said instruction buffer means and said instruction decoder means; each of said buses being divided into a field for said basic segment and a field for said expanded segment; marking providing means being provided for putting a control marking for each unit length in said instruction code string to identify the basic segment and non basic segment and to determine whether the different basic segments can be decoded simultaneously or not; said instruction buffer means including code storage means for reading out and storing at least said instruction code string; marking storage means for storing said marking; identifying means for identifying the leading position for leading out the instruction code to be output to the first one of said instruction decoders; and control circuit that determines whether the first basic segment at the leading position of reading out and subsequent other basic segment can be processed simultaneously by a common decoder or, not with reference to said control marking, assigns the instruction codes of said basic segments in said instruction code string to said fields for the basic segments in a plurality of buses, and assigns instruction codes in said expanded segments in said instruction code string to respective fields for the expanded segments in a plurality of said buses.

Claim 8

An instruction buffer device for processing an instruction code string that includes a basic segment including a code for distinguishing the type of instructions and expanded segment added depending upon a designation of the basic segment; said basic segment and said expanded segment respectively having lengths a multiple of a predetermined unit length; the length of said expanded segment being variable, and one or more said basic segments and said expended segments being combined to form one instruction; said instruction buffer device comprising: instruction buffer means reading out and storing said instruction code sting, a plurality of instruction decoders for simultaneously decoding a plurality of instructions and a plurality of buses connecting said instruction buffer means and said instruction decoder means; each of said buses being divided into a field for said basic segment and a field for said expanded segment; marking providing means being provided for putting a control marking for each unit length in said instruction code string to identify the basic segment and non basic segment and to determine whether the different basic segments can be decoded simultaneously or not; said instruction buffer means including code storage means for reading out and storing at least said instruction code string; marking storage means for storing said marking; identifying means for identifying the leading position for leading out the instruction code to be output to the first of said instruction decoders; and control circuit selecting the first basic segment at the leading position of reading out and the basic segment among the second basic segments following said first basic segment and having a marking indicating that it cannot be processed simultaneously by a common decoder, to output mutually independently to respective first basic segment fields of a plurality of buses outputting the instruction code of said second basic segment to the bus, to which the instruction code of one preceding basic segment is output when the marking for said second basic segment indicates that it can be simultaneously processed with one preceding basic segment by a common decoder, and when each basic segment has expanded segment, outputting the instruction code of the relevant expanded segments to one or more fields for the expanded segment in the bus, to which the corresponding basic segment is output.

Claim 9

An instruction buffer device as set forth in claim 8 that further comprises an output means for adjusting the output position so that the least significant bit of the instruction code of said expanded segment is output to the least significant bit of the field for the expanded segment in said bus.

Claim 10

A data processing system including an instruction buffer as defined in any one of the preceding claims, wherein the bus connected to said instruction decoder is constituted of one or more basic segment fields and one or more expanded segment fields; said decoder includes means for discriminating said expanded segment between an immediate or displacement and detecting the length thereof, and an immediate or displacement generation means, and wherein from the least significant bit of the selected expanded segment field, the code sting of the length designated by said decoder is extracted for the generation respectively of immediate or displacement.

Claim 11

A microprocessor characterized by an instruction buffer as defined in any one of the preceding claims.