EP0504946A1
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EP
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Vertical metal-oxide semiconductor device
Assignee: HP Inc
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Filing: 1992-03-23
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Granted: —
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Expires: 2012-03-23
Abstract
Abstract A vertical CMOS semiconductor structure and a method of making the structure. A polysilicon gate post (44) rises normal to a substrate (12). An annular semiconductor device (T1) surrounds the gate post (44). The device (T1) consists of a channel layer (16) sandwiched between a pair of source/drain layers (14, 18). Each layer lies directly above the layer beneath, with the gate post (44) projecting up through the layers. An additional semiconductor device (T2) of the same or differing polarities may be stacked above the first, the various devices being suitably spaced apart from each other. Electrical connections with the gate post (44) and the various source/drain layers may be configured to provide a complementary inverter or some other circuit as desired.
Inventors
- 👤 Dirk J. Barthelink
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 00:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/025; H10D30/60; H10D30/63; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/837; H10D84/85; H10D88/00; H10D88/01
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
114 words
A vertical metal-oxide semiconductor structure comprising: a generally horizontal substrate (12); a substantially vertical gate post (44) formed of conductive material and disposed above the substrate (12); and a first semiconductor device (T1) supported by and extending radially from the gate post (44), the device comprising: a channel region (16) surrounding the gate post (44); a gate oxide (42) disposed between the gate post (44) and the channel region (16); a lower source/drain region (14) below and attached to the channel region (16) ; and an upper source/drain region (18) above and attached to the channel region (16), the channel region (16) having an opposite polarity from that of the drain/source regions (14, 18).
Claim 2
Dependent Claim
103 words
A semiconductor structure as in claim 1 and further comprising a second semiconductor device (T2) supported by and extending radially from the gate post (44) and disposed above the first device (T1), the second device (T2)comprising: a channel region (26) surrounding the gate post (44); a gate oxide (42) disposed between the gate post (44) and the channel region (26); a lower source/drain region (24) below and attached to the channel region (26); and an upper source/drain region (28) above and attached to the channel region (26), the channel region (26) having an opposite polarity from that of the drain/source regions (24, 28).
Claim 3
Dependent Claim
35 words
A semiconductor structure as in claim 2 wherein one of the source/drain regions (18) of the first device (T1) is electrically connected (W1-72-W2) to one of the source/drain regions (24) of the second device (T2).
Claim 4
Dependent Claim
31 words
A semiconductor structure as in any preceding claim wherein the substrate (12) comprises a layer of insulating material (40) that electrically insulates the gate post (44) from any underlying material (12).
Claim 5
Dependent Claim
34 words
A semiconductor structure as in any preceding claim wherein the channel (16, 26) and source/drain regions (14, 18; 24, 28) of at least one of the devices (T1, T2) are formed of epitaxial material.
Claim 6
Dependent Claim
26 words
A semiconductor structure as in any preceding claim wherein one of the channel regions (16, 26) is sufficiently shallow to be fully depletable of majority carriers.
Claim 7
Independent Claim
248 words
A method of fabricating a metal-oxide semiconductor structure comprising: (a) forming, in order, on a substrate layer (12): a doped first lower source/drain layer (14), a doped first channel layer (16), and a doped first upper source/drain layer (18), the first channel layer (16) having an opposite polarity from that of the first source/drain layers (14, 18); lower and upper intermediate layers (20, 22); and a doped second lower source/drain layer (24), a doped second channel layer (26), and a doped second upper source/drain layer (28), the second channel layer (26) having an opposite polarity from that of the second source/drain layers (24, 28); (b) etching a hole (38) through the layers (14-28) and into the substrate (12); (c) forming an oxide layer (42) on the sides of the hole (38); (d) filling the hole (38) with conductive material to form a vertical gate post (44); (e) etching a trench (48) through the second upper source/drain layer (28) and through the second channel layer (26) down to the second lower source/drain layer (24), the trench (48) spaced a predetermined distance apart from the gate post (44), thereby defining an upper semiconductor device (T2); (f) removing the lower intermediate layer (20); and (g) etching a trench (64) through the first upper source/drain layer (18) and through the first channel layer (16) down to the first lower source/drain layer (14), the trench (64) spaced a predetermined distance apart from the gate post (44), thereby defining a lower semiconductor device (T1).
Claim 8
Dependent Claim
42 words
A method according to claim 7 wherein step (e) comprises: forming a spacer (34, 36) around the gate post (44); and using the spacer (34, 36) as a mask to determine the distance between the gate post (44) and the trench (48).
Claim 9
Dependent Claim
59 words
A method according to claim 7 or 8 wherein step (f) comprises: forming a spacer (52) around the upper semiconductor device (T2); etching a trench (54) through the upper intermediate layer (22); forming a spacer (56) around the spacer (52) and the remaining portion of the upper intermediate layer (22); and etching to remove the lower intermediate layer (20).
Claim 10
Dependent Claim
98 words
A method according to claim 7, 8 or 9 and further comprising forming an electrical connection between the first and second semiconductor devices (T1, T2) by: (h) forming a vertical conducting plug (72) generally parallel the gate post (44); (i) forming a first generally horizontal conducting strip (W1) between one of the layers (18, 16 or 14) of the first semiconductor device (T1) and the conducting plug (72); and (j) forming a second generally horizontal conducting strip (W2) between one of the layers (24, 26 or 28) of the second semiconductor device (T2) and the conducting plug (72).
References Cited (Backward Citations)
FR93427E
Cited
US4740826A
Cited
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