EP0504086A1
Expired / Lapsed
EP
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A three wire half duplex asynchronous communication architecture
Assignee: International Business Machines Corp
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Filing: 1992-02-11
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Granted: —
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Expires: 2012-02-11
Abstract
Abstract A controller and communications architecture for controlling the operation of computer I/O devices such as a keyboard or the like includes two microprocessors, a three-wire half duplex communications interface and a transmission protocol allow data transmission, error, detection and contention resolution. The transmission protocol allows the microprocessors to transmit serial data over the interface which includes a single shared data line and two simplex clock lines.
Inventors
- 👤 Dennis Arthur Cummins
- 👤 Wayne Roger Hucaby
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 02:29
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4247; G06F13/4256
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
225 words
A controller for use in a multi-key electronic key board characterized in that it comprises : a first microprocessor operatively coupled to scan keys on the multi-key electronic keyboard and to generate a coded signal representative of depressed keys; said first microprocessor further including - a first bidirectional data port, - a first unidirectional signal port, and - a second unidirectional signal port; a second microprocessor having a second bidirectional data port, a third unidirectional signal port and a fourth unidirectional signal port; a transmission data line for transmitting data bidirectionally interconnecting the first bidirectional data port and the second bidirectional data port; a transmission control line for transmitting control signals unidirectionally interconnecting the first unidirectional signal port and the second unidirectional signal port; a transmission control line for transmitting control signals unidirectionally interconnecting the third unidirectional signal port and the fourth unidirectional signal port; a first circuit means disposed in each microprocessor; said circuit means operatively tying interprocessor interconnecting lines to predetermined voltage signal levels; and a second means disposed in each microprocessor and operatively coupled to each of the interprocessor interconnecting lines; said second means causing a transmitting processor to sample electrical states on the transmission control line of a receiving processor and if said electrical state is one of the predetermined voltage signal levels, transmit data bits on the transmission data line.
Claim 2
Dependent Claim
43 words
The controller of Claim 1 wherein said second means causes the receiving microprocessor to energize its transmission control line with a predetermined pattern of pulses indicating that a bit on the data line has been received and indicating readiness to receive another bit.
Claim 3
Dependent Claim
46 words
The controller of Claim 1 or 2 wherein said second means causes the transmitting microprocessor to energize its transmission control line with a sequence of pulses similar but offset from the prede termined pattern of pulses on the transmission con trol line of said transmitting microprocessor.
Claim 4
Dependent Claim
45 words
The controller of Claim 1, 2 or 3 wherein the first circuit means includes a voltage source; a resistive means connected to the voltage source; and a "dot OR" circuit interconnection coupling each line to a transmit path and a receive path within a microprocessor.
Claim 5
Dependent Claim
22 words
The controller of anyone of claims 1 to 4, wherein the predetermined voltage signal levels are set to a value of 5V.
Claim 6
Dependent Claim
189 words
A communications interface for said interprocessor communication of claim 1 characterized in that it comprises : a bidirectional communications data line interconnecting a plurality of microprocessors; said bidirectional communications data line transmitting data bidirectionally; a first simplex control line for transmitting control information unidirectionally interconnecting the microprocessors; a second simplex control line for transmitting control information in a single direction interconnecting the microprocessors; and a third means disposed in each microprocessor and operatively coupled to each interconnecting lines; said third means causing a microprocessor desiring to communicate with another microprocessor to sample electrical signals on a simplex control line of said another microprocessor and if the electrical signals are at a first electrical state, said microprocessor lowering the bidirectional communications data line whereupon said another microprocessor sensing a lowered bidirectional communications data line forces electrical signals on its simplex control line to an electrical state opposite to that of the first electrical state and said microprocessor sensing a change in signal state on the simplex control line of said another microprocessor lowers electrical states on its simplex control line to indicate a start bit on the bidirectional data line.
Claim 7
Dependent Claim
16 words
The communications interface of Claim 6 wherein the first electrical state is a positive voltage level.
Claim 8
Dependent Claim
67 words
The communications interface of Claim 6 or 7 wherein said third means further causes a predetermined pattern of electrical pulses to be outputted on the simplex control line of-said microprocessor and the simplex control line of said another microprocessor; said predetermined pattern of electrical pulses indicating to a sending microprocessor that a bit has been received and indicating to a receiving processor that the bit is valid.
Claim 9
Independent Claim
224 words
A method for controlling the transmission of data among a plurality of interconnected processors char acterized in that it comprises the steps of: (a) interconnecting at least two of the processors with a bidirectional communications link used by either processor to transmit data, a first unidirectional communications link used by one of the processors to transmit control signals and a second unidirectional communications link used by another of the processors to transmit control signals; (b) when a processor desires to send data to another processor, said processor (i) testing the unidirectional communications link of said another processor to see if it is set to a first pre-determined electrical state, (ii) lowering the bidirectional communications link, if said unidirectional link of said another processor is set to the first predetermined electrical state; (c) on sensing a lowered bidirectional communica tions link, said another processor lowering its unidirectional communications link to indicate its readiness to receive data; (d) on sensing that said another processor lowers its unidirectional communications link, said processor lowering its unidirectional communi cations link indicating a valid start bit; (e) said another processor then raising its unidi rectional communications link lowered in step (c) to indicate receipt of the start bit; and (f) said processor raising its unidirectional communications link lowered in step (d) and waits for said another processor to request data.
References Cited (Backward Citations)
EP0239155A1
Cited
DE3937807A1
Cited
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