Contact structure of an interconnection layer placed on a surface having steps and SRAM having a multilayer interconnection and manufacturing method thereof

Claim 2

The device of claim 1, wherein said intermediate conductive layer is of a material preventing formation of a pn junction between said interconnection layer and said interconnection contact portion.

Claim 3

The device of claim 1, wherein said intermediate conductive layer is of a material doped to be more highly conductive than said interconnection layer and said silicon plug.

Claim 4

The semiconductor device of claim 1, wherein said intermediate conductive layer is positioned on the flat upper surface of said silicon plug in said contact hole.

Claim 5

The semiconductor device of claim 4, wherein said flat upper surface of said silicon plug is positioned generally at the level of an upper surface of said interlevel insulating layer.

Claim 6

The semiconductor device of claim 1, including an additional conductor layer in said interlevel insulating layer and having a portion exposed through a sidewall of said contact hole.

Claim 7

The semiconductor device of claim 6, wherein said intermediate conductive layer is in contact with said contact portion.

Claim 8

The semiconductor device of claim 1, including a pad layer of polysilicon of diameter greater than the diameter of said contact hole, said silicon plug being in contact with said pad layer in said contact hole.

Claim 9

A semiconductor device having an interconnection contact portion comprising: a silicon layer (2); an interlevel insulating layer (9) formed on a surface of said silicon layer; a contact hole (16) formed in said interlevel insulating layer; a silicon plug layer (15) embedded within said contact hole; an intermediate conductive layer (11) formed of either refractory metal or refractory metal silicide formed on a surface of said silicon plug layer; and an interconnection layer (8a) of polycrystalline silicon formed on a surface of said interlevel insulating layer and connected to said intermediate conductive layer.

Claim 10

The semiconductor device having an interconnection contact portion according to claim 9, wherein said silicon layer and said silicon plug layer comprise impurity of the same conductivity type; and said interconnection layer comprises impurity of a conductivity type different from that of impurity included in said silicon plug layer.

Claim 11

The semiconductor device having an interconnection contact portion according to claim 9, wherein said silicon plug layer is formed of polycrystalline silicon.

Claim 12

The semiconductor device having an interconnection contact portion according to claim 9, wherein said silicon plug layer is formed of single-crystalline silicon.

Claim 13

The semiconductor device having an interconnection contact portion according to claim 9, wherein said silicon layer comprises a silicon substrate (1) including an impurity region (7); and said silicon plug layer is connected to said impurity region formed in said silicon substrate.

Claim 14

An SRAM comprising memory cells, each including a pair of first and second CMOS inverters connected so as to constitute a flip-flop circuit, and first and second MOS transfer transistors connected to node points of the flip-flop circuit, respectively, said first CMOS inverter comprising a first MOS drive transistor of a first conductivity type (20a) formed on a main surface of a silicon substrate, and a first thin film transistor of a second conductivity type (21a) formed on a surface of an interlevel insulating layer formed on said main surface of the silicon substrate, said second CMOS inverter comprising a second MOS drive transistor of the first conductivity type (20b) formed on the main surface of the silicon substrate, and a second thin film transistor of the second conductivity type (21b) formed on said surface of the interlevel insulating layer, and said first MOS transfer transistor and said second MOS transfer transistor being formed on the main surface of said silicon substrate (1), said SRAM comprising: first interconnection means for connecting a gate electrode of said first MOS drive transistor, a source/drain region of said second MOS transfer transistor, and a source/drain region of said second thin film transistor; and second interconnection means for connecting a gate electrode of said second MOS drive transistor, a source/drain region of said first MOS transfer transistor, and a source/drain region of said first thin film transistor; said first interconnection means being embedded in an opening (16) formed in said interlevel insulating layer and comprising a silicon plug layer (15) connected to a gate electrode (6) of said first MOS drive transistor and to a source/drain region (7) of said second MOS transfer transistor, an intermediate conductive layer (11) of either refractory metal or refractory metal silicide formed on a surface of said silicon plug layer, and an interconnection layer (8a) of polycrystalline silicon extending on a surface of said interlevel insulating layer and electrically connecting said intermediate conductive layer and a source/drain region of said second thin film transistor, and said second interconnection means being embedded in the opening formed in said interlevel insulating layer and comprising a silicon plug layer (15) connected to a gate electrode of said second MOS drive transistor and to a source/drain region of said first MOS transfer transistor, an intermediate conductive layer of either refractory metal or refractory metal silicide formed on the surface of said silicon plug layer, and an interconnection layer of polycrystalline silicon extending on a surface of said interlevel insulating layer and electrically connecting said intermediate conductive layer and a source/drain region of said first thin film transistor.

Claim 15

The SRAM according to claim 14, wherein said silicon plug layer comprises impurity of a conductivity type different from that of said interconnection layer.

Claim 16

The SRAM according to claim 15, wherein said silicon plug layer is formed of either polycrystalline silicon or single-crystalline silicon.

Claim 18

The method of manufacturing a semiconductor device according to claim 17, wherein said step of introducing impurity into the silicon plug layer comprises a step of implanting impurity into said silicon plug layer using an ion implantation method with ion implantation energy of more than 150keV.

Claim 19

A manufacturing method of a semiconductor device, comprising the steps of: forming an interlevel insulating layer (9) on a surface of a first silicon layer (1); forming an opening (16) reaching said surface of the first silicon layer in said interlevel insulating layer; forming a refractory metal silicide layer (100) on said surface of the first silicon layer; forming a second silicon layer (110a) on a surface of said interlevel insulating layer and within said opening; etching-back said second silicon layer and forming a silicon plug layer (110b) of said second silicon layer within said opening; introducing impurities (19) into said silicon plug layer; and forming an interconnection layer (8a) by forming and patterning a polycrystalline silicon layer on the surface of said interlevel insulating layer and a surface of said silicon plug layer.

Claim 20

A manufacturing method of a semiconductor device, comprising the steps of: forming an interlevel insulating layer (9) on a surface of a first silicon layer (1); forming an opening (16) reaching said surface of the first silicon layer in said interlevel insulating layer; forming a second silicon layer (15a) on a surface of said interlevel insulating layer and within said opening; etching-back said second silicon layer and forming a silicon plug layer (15) of said second silicon layer within said opening; introducing impurities (18a) into said silicon plug layer; forming an impurity layer (120) of a high concentration including impurities in a concentration higher than that of impurities included in said silicon plug layer on a surface of said silicon plug layer; and forming an interconnection layer (8a) by forming and patterning a polycrystalline silicon layer on the surface of said interlevel insulating layer and a surface of said impurity layer of a high concentration.