Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
301 words
A memory cell array divided type multi-port memory device having random access means and serial access means, comprising: a plurality of cell array sections (14A-14D) each having a plurality of memory cells (C) disposed in a matrix form, said plurality of cell array sections (14A-14D) being disposed in a column direction at a predetermined pitch, each said cell array section (14A-14D) having a plurality of word lines (WL) and bit lines (BL), said word lines (WL) being connected to said memory cells (C) disposed in a row direction for selection of said connected memory cells (C), and said bit lines (BL) being connected to said memory cells (C) disposed in a column direction for data transfer to and from said selected memory cells (C); a row decoder (RD) for activating a desired one of said word lines (WL); sense amplifier means (13A-13D) provided for each said bit line (BL) for sensing data read out to each said bit line (BL); a RAM port (DQ) connected to said bit lines (BL) via RAM transfer gates (RG); a column decoder (12AB, 12CD) for selectively turn on/off said RAM transfer gates (RG); a plurality of data transfer lines (A) each having a data transfer gate (TRG1, TRG2) at the intermediate position thereof, said data transfer lines (A) being connected to said bit lines (BL) and formed on a layer different from layers of said word lines (WL) and bit lines (BL); data transfer gate control means (TGC) for turning on/off a desired one of said data transfer gates (TRG1, TRG2); a plurality of serial registers (15) connected to said data transfer lines (A); a serial port (SQ) connected via each serial transfer gate (SG) to each said serial register (15); and a serial decoder (16) for serially turning on/off said serial transfer gates (SG).
Claim 2
Dependent Claim
23 words
A multi-port memory device according to claim 1, wherein random access to said cell array sections (14A-14D) is executed asynchronously with serial access.
Claim 3
Dependent Claim
21 words
A multi-port memory device according to claim 1, wherein the number of said cell array sections (14A-14D) is at least three.
Claim 4
Dependent Claim
41 words
A multi-port memory device according to claim 3, wherein substantially two halves of said cell array sections (14A-14D) are disposed respectively at the right and left sides of said serial registers (15) and said serial decoder (16) in a column direction.
Claim 5
Dependent Claim
32 words
A multi-port memory device according to claim 3 or 4, wherein said word lines (WL), said bit lines (BL), and said data transfer lines (A), are formed on three different layers, respectively.
Claim 6
Dependent Claim
25 words
A multi-port memory device according to claim 1 or 5, wherein said sense amplifier means (13A-13D) is provided for each said cell array section (14A-14D).
Claim 7
Dependent Claim
23 words
A multi-port memory device according to claim 1, wherein said sense amplifier means (13A-13D) is provided for each said cell array sections (14A-14D).
Claim 8
Dependent Claim
58 words
A multi-port memory device according to claim 6, wherein an initial sense portion (13CD 2L , 13CD 2R ) of said sense amplifier means (13A-13D) is provided for each said cell array section (14A-14D), and one restore portion (13CD₁) of said sense amplifier means (13A-13D) is provided in common for the plurality of said cell array sections (14A-14D).
Claim 9
Dependent Claim
36 words
A multi-port memory device according to claim 1 or 6, wherein said row decoder (RD) activates a desired one of said word lines (WL) in one of said cell array sections (14A-14D) during one access cycle.
Claim 10
Dependent Claim
72 words
A multi-port memory device according to claim 1 or 9, wherein in a data transfer cycle between said selected memory cells (C) and said serial registers (15), said data transfer gate control means (TGC) turns on only said data transfer gates (TRG1, TRG2) on said data transfer lines (A) connecting said serial registers (15) to said bit lines (BL) in said cell array section (14A-14D) belonging to said selected memory cells (C).