Bipolar transistor structure & BICMOS IC fabrication process

Claim 2

An integrated circuit bipolar NPN transistor structure having collector (C), base (B) and emitter (E) regions formed in the surface of an epitaxial layer (EPI) of semiconductor material deposited over a substrate (SUB), said bipolar transistor structure having a buried collector layer (BCL) formed in the substrate underlying the collector (C), base (B) and emitter (E) regions, said buried collector layer (BCL) comprising relatively slow diffusing BCL N type atoms separated from said base and emitter regions by semiconductor material of the epitaxial layer (EPI), and a collector sink region (CS) formed in the epitaxial layer electrically coupling the collector region (C) with the buried collector layer (BCL), said emitter region being formed in the base region with an active base region layer (ABL) below the emitter region, and a surface spacer region (CBSS) separating the collector region (C) and base region (B), the improvement comprising: a subemitter collector region (SEC) formed in the buried collector layer (BCL) underlying the emitter region (E) and active base region layer (ABL), said subemitter collector region comprising relatively fast diffusing N type atoms distributed in a retrograde concentration upward from the buried collector layer (BCL) into the epitaxial layer (EPI).

Claim 3

The bipolar transistor structure of claim 1 wherein the subemitter collector region (SEC) comprises said relatively fast diffusing N type atoms distributed in a retrograde concentration upward from the buried collector layer (BCL) to the active base region layer (ABL) below the emitter region (E).

Claim 4

The bipolar transistor structure of claim 1 wherein the subemitter collector region (SEC) comprises semiconductor material with an N+ concentration of phosphorous atoms in the buried collector layer (BCL) and a retrograde concentration of phosphorus atoms distributed upward from the buried collector layer (BCL) into the epitaxial layer (EPI).

Claim 5

The bipolar transistor structure of claim 1 wherein the subemitter collector region (SEC) occupies a horizontal cross section area approximately 10% to 20% of the horizontal cross section area of the buried collector layer (BCL).

Claim 6

The bipolar transistor structure of claim 1 wherein the surface spacer region (CBSS) between the collector (C) and base (B) regions comprises field oxide.

Claim 7

A BICMOS integrated circuit structure comprising at least one bipolar NPN transistor structure having collector (C), base (B) and emitter (E) regions formed in the surface of an epitaxial layer (EPI) of semiconductor material deposited over a substrate (SUB), said bipolar transistor structure having a buried collector layer (BCL) formed in the substrate underlying the collector, base and emitter regions, said buried collector layer comprising relatively slow diffusing BCL N type atoms separated from said base (B) and emitter (E) regions by semiconductor material of the epitaxial layer (EPI), and a collector sink region (CS) formed in the epitaxial layer electrically coupling the collector region (C) with the buried collector layer (BCL) said emitter region being farmed in the base region with an active base region layer (ABL) below the emitter region (E), and a surface spacer region separating the collector region (C) and base region (B), said bipolar transistor structure being isolated in the BICMOS integrated circuit structure by isolation oxide regions (ISOX), and at least one CMOS transistor structure having source (S) and drain (D) regions formed in the epitaxial layer (EPI) separated by a channel region with a gate (G) formed over the channel region separated by a gate oxide layer (GOX), and an N well formed in the substrate underlying the source (S) drain (D) and channel regions, said CMOS transistor structure being framed by field oxide regions (FOX), the improvement comprising: said bipolar transistor structure having a subemitter collector region (SEC) formed in the buried collector layer (BCL) underlying the emitter region (E) and active base region layer (ABL), said subemitter collector region comprising relatively fast diffusing N type atoms distributed in a retrograde concentration upward from the buried collector layer (BCL) into the epitaxial layer (EPI) to the active base layer region (ABL); said CMOS transistor structure having a retro N well (NWELL) comprising the relatively fast diffusing N type atoms distributed in a retrograde concentration upward from the substrate (SUB) into the epitaxial layer (EPI) to the source (S), drain (D) and channel regions.

Claim 8

A BICMOS integrated circuit structure comprising at least one bipolar NPN transistor structure having collector (C), base (B) and emitter (E) regions formed in the surface of an epitaxial layer (EPI) of semiconductor material deposited over a substrate (SUB), said bipolar transistor structure having a buried collector layer (BCL) formed in the substrate underlying the collector, base and emitter regions, said buried collector layer comprising relatively slow diffusing BCL N type atoms separated from said base (B) and emitter (E) regions by semiconductor material of the epitaxial layer (EPI), and a collector sink region (CS) formed in the epitaxial layer electrically coupling the collector region (C) with the buried collector layer (BCL) said emitter region being farmed in the base region with an active base region layer (ABL) below the emitter region (E), and a surface spacer region separating the collector region (C) and base region (B), said bipolar transistor structure being isolated in the BICMOS integrated circuit structure by isolation oxide regions (ISOX), and at least one CMOS transistor structure having source (S) and drain (D) regions formed in the epitaxial layer (EPI) separated by a channel region with a gate (G) formed over the channel region separated by a gate oxide layer (GOX), and an N well formed in the substrate underlying the source (S) drain (D) and channel regions, said CMOS transistor structure being framed by field oxide regions (FOX), the improvement comprising: said bipolar transistor structure having a subemitter collector region (SEC) formed in the buried collector layer (BCL) underlying the emitter region (E) and active base region layer (ABL), said subemitter collector region comprising relatively fast diffusing N type atoms distributed in a retrograde concentration upward from the buried collector layer (BCL) into the epitaxial layer (EPI) to the active base layer region (ABL); said CMOS transistor structure having a retro N well (NWELL) comprising the relatively fast diffusing N type atoms distributed in a retrograde concentration upward from the substrate (SUB) into the epitaxial layer (EPI) to the source (S), drain (D) and channel regions.

Claim 9

The BICMOS IC structure of claim 6 wherein the subemitter collector region (SEC) comprises a localized N+ concentration of phosphorus atoms in the base collector layer (BCL) and a retrograde concentration of phosphorus atoms distributed upward from the buried collector layer (BCL) into the epitaxial layer (EPI) to the active base region layer (BL), and wherein the retro N well (NWELL) comprises an N+ concentration of phosphorus atoms in the substrate and a retrograde concentration of phosphorus atoms distributed upward from the substrate (S) into the epitaxial layer (EPI) to the source (S), drain (D) and channel regions.

Claim 10

The BICMOS IC structure of claim 6 wherein the subemitter collector region (SEC) occupies a horizontal cross section area approximately 10% to 20% of the horizontal cross section area of the buried collector layer (BCL).

Claim 11

The BICMOS IC structure of claim 6 wherein the surface spacer region (CBSS) separating the collector (C) and base (B) regions comprises field oxide.

Claim 12

A BICMOS process for fabrication of at least one bipolar transistor structure and at least one CMOS transistor structure in a BICMOS integrated circuit (IC), said bipolar transistor structure having collector (C), base (B) and emitter (E) regions formed in an epitaxial layer (EPI) of semiconductor material deposited over a substrate (SUB), said bipolar transistor structure having a buried collector layer (BCL) formed in the substrate using a BCL definition mask, etch and implant sequence before deposition of the epitaxial layer, said buried collector layer (BCL) underlying the collector, base and emitter regions and comprising relatively slow diffusing BCL N type atoms separated from the base (B) and emitter (E) regions by semiconductor materials of the epitaxial layer (EPI), said emitter region (E) being formed in the base region (B) with an active base region layer (ABL) below the emitter region, said bipolar transistor structure being isolated by isolation oxide regions (ISOX), said CMOS transistor structure having source (S) and drain (D) regions formed in the epitaxial layer (EPI), said source and drain regions being separated by a channel region with a gate (G) formed over the channel region separated by a gate oxide layer (GOX), and an N well (NWELL) of semiconductor material formed in the substrate underlying the source, drain and channel regions, said CMOS transistor structure being framed by field oxide regions (FOX) formed using a field oxide definition mask, said BICMOS process comprising: forming the N well (NWELL) of the CMOS transistor structure in the substrate (SUB) using an N well definition mask, etch and implant sequence before deposition of the epitaxial layer, and after forming the buried collector layer (BCL) of the bipolar transistor structure in the substrate, said step of forming the N well comprising implanting relatively fast diffusing N type atoms through an N well defining opening in the N well definition mask and into the substrate; constructing the N well definition mask also as a subemitter collector (SEC) definition mask with an SEC defining opening over the buried collector layer of the bipolar transistor structure and implanting the relatively fast diffusing N type atoms to form a subemitter collector region (SEC) in the buried collector layer (BCL) of the bipolar transistor structure at the same time as implanting the N well of the CMOS transistor structure.

Claim 13

A BICMOS process for fabrication of at least one bipolar transistor structure and at least one CMOS transistor structure in a BICMOS integrated circuit (IC), said bipolar transistor structure having collector (C), base (B) and emitter (E) regions formed in an epitaxial layer (EPI) of semiconductor material deposited over a substrate (SUB), said bipolar transistor structure having a buried collector layer (BCL) formed in the substrate using a BCL definition mask, etch and implant sequence before deposition of the epitaxial layer, said buried collector layer (BCL) underlying the collector, base and emitter regions and comprising relatively slow diffusing BCL N type atoms separated from the base (B) and emitter (E) regions by semiconductor materials of the epitaxial layer (EPI), said emitter region (E) being formed in the base region (B) with an active base region layer (ABL) below the emitter region, said bipolar transistor structure being isolated by isolation oxide regions (ISOX), said CMOS transistor structure having source (S) and drain (D) regions formed in the epitaxial layer (EPI), said source and drain regions being separated by a channel region with a gate (G) formed over the channel region separated by a gate oxide layer (GOX), and an N well (NWELL) of semiconductor material formed in the substrate underlying the source, drain and channel regions, said CMOS transistor structure being framed by field oxide regions (FOX) formed using a field oxide definition mask, said BICMOS process comprising: forming the N well (NWELL) of the CMOS transistor structure in the substrate (SUB) using an N well definition mask, etch and implant sequence before deposition of the epitaxial layer, and after forming the buried collector layer (BCL) of the bipolar transistor structure in the substrate, said step of forming the N well comprising implanting relatively fast diffusing N type atoms through an N well defining opening in the N well definition mask and into the substrate; constructing the N well definition mask also as a subemitter collector (SEC) definition mask with an SEC defining opening over the buried collector layer of the bipolar transistor structure and implanting the relatively fast diffusing N type atoms to form a subemitter collector region (SEC) in the buried collector layer (BCL) of the bipolar transistor structure at the same time as implanting the N well of the CMOS transistor structure.

Claim 14

The BICMOS process of claim 10 wherein the relatively fast diffusing N type atoms implanted in the subemitter collector region (SEC) of the bipolar transistor structure and in the N well (NWELL) of the CMOS transistor structure are phosphorus atoms and wherein the step of implanting the phosphorus atoms comprises implanting an N+ concentration of phosphorus atoms in the subemitter collector region and N well.

Claim 15

The BICMOS process of claim 10 comprising at least one annealing step after deposition of the epitaxial layer (EPI), formation of the source (S), drain (D) and channel regions of the CMOS transistor structure in the epitaxial layer, and formation of the collector (C), base (B) and emitter (E) regions of the bipolar transistor structure in the epitaxial layer, said annealing step comprising up diffusion of the relatively fast N type atoms from the N well to form a retro N well (NWELL) having a retrograde concentration of said N type atoms distributed from the substrate (SUB) through the epitaxial layer (EPI) to the source (S), drain (D) and channel regions in the CMOS transistor structure, and up diffusion of the relatively fast diffusing N type atoms implanted in the buried collector layer (BCL) forming a subemitter collector region (SEC) comprising a retrograde concentration of said N type atoms distributed from the base collector layer (BCL) through the active epitaxial layer (EPI) to the active base region layer (ABL).

Claim 16

The BICMOS process of claim 12 wherein the retrograde concentration of N type atoms in the subemitter collector region ranges from approximately n x 10 17 atoms/cm 3 at the buried collector layer (BCL) to n x 10 16 atoms/cm 3 at the base region layer (ABL) where n is approximately equal to 6.

Claim 17

The BICMOS process of claim 10 wherein the step of implanting relatively fast diffusing N type atoms to form a subemitter collector region in the buried collector layer comprises implanting and forming the subemitter collector region (SEC) with a horizontal cross section area limited to approximately 10% to 20% of the horizontal cross section area of the buried collector layer (BCL).

Claim 18

The BICMOS process of claim 10 further comprising the step of constructing the field oxide definition mask also as a collector base surface spacer region definition mask with a CBSS defining opening over the bipolar transistor structure, and defining and growing a field oxide surface spacer region (CBSS) separating the collector region (C) from the base region (B) of the bipolar transistor element.

Claim 19

The BICMOS process of claim 15 comprising the further step of using the field oxide collector base surface spacer region (CBSS) as part of a self-aligned transistor mask comprising the collector, emitter and base contact definition mask.

Claim 20

The BICMOS process of claim 12 wherein the retrograde concentration of N type atoms of the subemitter collector region (SEC) provides a net concentration of N type carriers at the junction of the active base region layer (BL) and the subemitter collector region (SEC) of approximately 6 x 10 16 atoms/CM 3 .

Claim 21

BICMOS integrated circuit (IC) photodefinition mask means for fabrication of bipolar transistor structures and CMOS transistor structures in IC bipolar transistor active areas and CMOS transistor active areas, said bipolar transistor structures having collector (C), base (B) and emitter (E) regions formed in an epitaxial layer (EPI) and a buried collector layer (BCL) underlying the collector, base and emitter regions, said CMOS transistor structures having source (S) and drain (D) regions separated by a channel region formed in the epitaxial layer (EPI) and an underlying N well, comprising: a retro N well photodefinition mask comprising a first mask layer formed with N well definition openings for implanting a retro N well in CMOS transistor active areas, said retro N well definition mask also comprising a subemitter collector definition mask being formed with subemitter collector definition openings through said first mask layer for implanting a subemitter collector region (SEC) in the buried collector layer (BCL) of bipolar transistor active areas at a location positioned to be below the emitter region (E) of bipolar transistor structures to be fabricated, said N well definition and subemitter collector definition mask being constructed for implanting the retro N well in CMOS transistor active areas and the subemitter collector in bipolar transistor active areas at the same time.

Claim 22

BICMOS integrated circuit (IC) photodefinition mask means for fabrication of bipolar transistor structures and CMOS transistor structures in IC bipolar transistor active areas and CMOS transistor active areas, said bipolar transistor structures having collector (C), base (B) and emitter (E) regions formed in an epitaxial layer (EPI) and a buried collector layer (BCL) underlying the collector, base and emitter regions, said CMOS transistor structures having source (S) and drain (D) regions separated by a channel region formed in the epitaxial layer (EPI) and an underlying N well, comprising: a retro N well photodefinition mask comprising a first mask layer formed with N well definition openings for implanting a retro N well in CMOS transistor active areas, said retro N well definition mask also comprising a subemitter collector definition mask being formed with subemitter collector definition openings through said first mask layer for implanting a subemitter collector region (SEC) in the buried collector layer (BCL) of bipolar transistor active areas at a location positioned to be below the emitter region (E) of bipolar transistor structures to be fabricated, said N well definition and subemitter collector definition mask being constructed for implanting the retro N well in CMOS transistor active areas and the subemitter collector in bipolar transistor active areas at the same time.

Claim 23

The BICMOS IC photodefinition mask means of claim 18 wherein the subemitter collector definition openings in the retro N well photodefinition mask have an area approximately 10% to 20% of the horizontal cross section area of the buried collector layer (BCL).

Claim 24

The BICMOS IC photodefinition mask means of claim 19 further comprising: a field oxide definition mask comprising a second mask layerformed with openings defining framing field oxide regions for framing the CMOS transistor active areas, said field oxide definition mask also comprising a surface spacer region definition mask formed with openings defining collector base surface spacer regions (CBSS) for separating collector regions and base regions in bipolar transistor structures of the bipolar transistor active areas.