EP0499985A2
Expired / Lapsed
EP
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Manufacturing method of semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1992-02-14
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Granted: —
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Expires: 2012-02-14
Abstract
Abstract A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film (22) and a gate oxide film (21) on a semiconductor substrate (20), depositing a first conductive layer (23) on an entire surface of the resultant structure, selectively etching the first conductive layer (23) located in a region other than an element region, oxidation of the entire surface of the resultant structure, depositing a second conductive layer (27) on an entire surface of the resultant structure, and etching the first conductive layer (23), the oxide film (26), and the second conductive layer (27) using the same mask to form a plurality of floating gates by the first conductive layer (23) and to form a plurality of control gates by the second conductive layer (27), wherein the step of selectively etching the first conductive layer (23) includes the first etching step of forming cell slits (24) for separating the plurality of floating gates from each other and the second etching step of forming removed regions (25) each of which includes only one end of each of the plurality of control gates.
Inventors
- 👤 Yukihiro C/O Intellectual Property Div. Saeki
- 👤 Osamu C/O Intellectual Property Div. Matsumoto
- 👤 Masayuki C/O Intellectual Property Div. Yoshida
- 👤 Takahide C/O Intellectual Property Div. Mizutani
- 👤 Nobuyoshi c/o Intellectual Property Div. Chida
- 👤 Tomohisa c/o Intellectual Prop. Div. Shigematsu
- 👤 Teruo C/O Intellectual Property Div. Uemura
- 👤 Kenji c/o Intellectual Property Div. Toyoda
- 👤 Hiroyuki c/o Intellectual Property Div. Takamura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 04:45
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; Y; Y10; Y10S; Y10S148/00; Y10S148/106
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
178 words
A manufacturing method of a semiconductor memory device, comprising the steps of: selectively forming a field oxide film (22) and a gate oxide film (21) on a semiconductor substrate (20); depositing a first conductive layer (23) on an entire surface of the resultant structure; selectively etching said first conductive layer (23) located in a region other than an element region; depositing a second conductive layer (27) on an entire surface of the resultant structure; and etching said first conductive layer (23) and said second conductive layer (27) using the same mask to form a plurality of floating gates (62) by said first conductive layer (23) and to form a plurality of control gates (63) by said second conductive layer (27); wherein the step of selectively etching said first conductive layer (23) includes the first etching step of removing cell slits (24) for separating said plurality of floating gates (62) from each other and the second etching step of forming removed regions (25) each of which includes only one end of each of said plurality of control gates (63).
Claim 2
Dependent Claim
19 words
A manufacturing method according to claim 1, characterized in that the first and second etching steps are simultaneously performed.
Claim 3
Dependent Claim
38 words
A manufacturing method according to claim 1, characterized in that each of said removed regions (25) each of which includes one end of each of said control gates (63) includes a part or all of a contact region.
Claim 4
Dependent Claim
192 words
A manufacturing method of a semiconductor memory device, comprising the steps of: selectively forming a field oxide film (22) and a gate oxide film (21) on a semiconductor substrate (20); depositing a first conductive layer (23) on an entire surface of the resultant structure; selectively etching said first conductive layer (23) located in a region other than an element region; depositing a second conductive layer (27) on an entire surface of the resultant structure; and etching said first conductive layer (23) and said second conductive layer (27) using the same mask to form a plurality of floating gates by said first conductive layer (23) and to form a plurality of control gates by said second conductive layer (27); wherein the step of selectively etching said first conductive layer (23) includes the first etching step of forming cell slits (24) for separating said plurality of floating gates (62) from each other and the second etching step of forming removed regions (25) each of which includes only one end of each of said plurality of control gates (63), and the first and second etching steps are performed using etching methods different from each other.
Claim 5
Dependent Claim
33 words
A manufacturing method according to claim 4, characterized in that the first etching step is performed by an anisotropic etching method, and the second etching step is performed by an isotropic etching method.
Claim 6
Dependent Claim
38 words
A manufacturing method according to claim 4, characterized in that each of said removed regions (25) each of which includes one end of each of said control gates (63) includes a part or all of a contact region.
Claim 7
Dependent Claim
177 words
A manufacturing method of a semiconductor memory device, comprising the steps of: selectively forming a field oxide film (22) and a gate oxide film (21) on a semiconductor substrate (20); depositing a first conductive layer (23) on an entire surface of the resultant structure; selectively etching said first conductive layer (23) located in a region other than an element region; depositing said second conductive layer (27) on an entire surface of the resultant structure; and etching said first conductive layer (23) and said second conductive layer (27) using the same mask to form a plurality of floating gates by said first conductive layer (23) and to form a plurality of control gates by said second conductive layer (27); wherein the step of selectively etching said first conductive layer (23) includes the anisotropic first etching step of forming cell slits (24) for separating said plurality of floating gates (62) from each other and the isotropic second etching step of forming removed regions (25) each of which includes only one end of each of said plurality of control gates.
References Cited (Backward Citations)
No citation records indexed.
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