Cache memory processing instruction data and data processor including the same

Claim 2

A cache memory as set forth in claim 1, wherein the instruction storing means comprises: a memory means (126) for storing an instruction fed from the memory and a corresponding instruction length information obtained by the instruction length decoding means; and means (125) for reading a corresponding instruction and an instruction length information thereof from the memory means in the cache hit state and transmitting the read data to the control means, and for receiving a corresponding instruction from the memory and an instruction length information thereof from the instruction length decoding means in the cache miss state and writing the received data into the memory means.

Claim 3

A cache memory as set forth in claim 2, further comprising means (123) for receiving a corresponding instruction from the memory and an instruction length information thereof from the instruction length decoding means in the cache miss state and transmitting the received data to the control means.

Claim 4

A cache memory as set forth in claim 2, wherein the instruction length decoding means comprises: means (211∼214) for latching a variable length instruction data fed from the memory, with divided into a plurality of data blocks; means (221∼224, 231∼234) for decoding an instruction format and an effective address from the respective instruction data for every data block; means (241∼244) for determining respective instruction lengths based on the decoded results for every data block; means (250) for generating an instruction length information for the latched variable length instruction data based on the respective determined instruction lengths, and generating a control signal for indicating which block of the plurality of data blocks is at the head of the variable length instruction; and means (260), responsive to the control signal, for controlling the instruction length determining means to be enable or disable.

Claim 5

A cache memory as set forth in claim 4, further comprising a cache hit/miss judging means (116) for judging whether the cache memory encounters the cache hit state or the cache miss state.

Claim 6

A cache memory as set forth in claim 5, wherein the cache hit/miss judging means comprises means (117) for retaining a comparison address and means (118) for comparing an instruction address fed from the control means with the comparison address to thereby judge whether the cache memory encounters the cache hit state or the cache miss state.

Claim 7

A data processor comprising: a processing means (20) for outputting an instruction address and fetching a variable length instruction; and a cache memory (10,100) connected between the processing means and a main memory, the cache memory including: an instruction length decoding means (11,121) for decoding an instruction length of the variable length instruction taken from the main memory; and an instruction storing means (12,122) for storing the variable length instruction from the main memory, together with an instruction length information obtained by the instruction length decoding means, wherein the variable length instruction and the instruction length information thereof are fed to the processing means.

Claim 8

A data processor as set forth in claim 7, wherein the processing means comprises: means (303) for storing a train of instruction codes (C) constituted by one set consisting of a basic part and an extended part or a combination of a plurality of sets; means (315) for judging whether data of every unit length in the train of instruction codes is a basic part to thereby append a control mark (M) thereto; means (316) for storing the control mark; means (307) for designating a head position of a predetermined train of instruction codes to be selectively output from the code storing means; means (317), responsive to outputs of the head position designating means and the mark storing means, for designating an output position of the predetermined train of instruction codes; means (308), responsive to outputs of the output position designating means and the mark storing means, for selectively outputting the predetermined train of instruction codes from the code storing means; means (309) for decoding instruction codes output from the selective outputting means; means (310) for storing the predetermined train of instruction codes output from the selective outputting means; means (312), responsive to outputs of the decoding means and the storing means, for generating an immediate value or a displacement value; and means (313) for executing an instruction based on outputs of the generating means.

Claim 9

A data processor as set forth in claim 8, wherein the instruction storing means comprises: a memory means (126) for storing an instruction fed from the memory and a corresponding instruction length information obtained by the instruction length decoding means; and means (125) for reading a corresponding instruction and an instruction length information thereof from the memory means in the cache hit state and transmitting the read data to the control means, and for receiving a corresponding instruction from the memory and an instruction length information thereof from the instruction length decoding means in the cache miss state and writing the received data into the memory means.

Claim 10

A data processor as set forth in claim 9, further comprising means (123) for receiving a corresponding instruction from the memory and an instruction length information thereof from the instruction length decoding means in the cache miss state and transmitting the received data to the control means.

Claim 11

A data processor as set forth in claim 9, wherein the instruction length decoding means comprises means (211∼214) for latching a variable length instruction data fed from the memory, with divided into a plurality of data blocks; means (221∼224, 231∼234) for decoding an instruction format and an effective address from the respective instruction data for every data block; means (241∼244) for determining respective instruction lengths based on the decoded results for every data block; means (250) for generating an instruction length information for the latched variable length instruction data based on the respective determined instruction lengths, and generating a control signal for indicating which block of the plurality of data blocks is at the head of the variable length instruction; and means (260), responsive to the control signal, for controlling the instruction length determining means to be enable or disable.

Claim 12

A data processor as set forth in claim 7, wherein the processing means comprises: means (303) for storing a train of instruction codes (C) constituted by one set consisting of a basic part and an extended part or a combination of a plurality of sets; means (315) for judging whether data of every unit length in the train of instruction codes is a basic part to thereby append a control mark (M) thereto; means (316) for storing the control mark; means (307a) for designating a head position of a predetermined train of instruction codes to be selectively output from the code storing means, by means of two read ports; means (317), responsive to outputs of the head position designating means and the mark storing means, for designating an output position of the predetermined train of instruction codes; a pair of output selecting units (308a,308b), responsive to outputs of the output position designating means and the mark storing means, each for selectively outputting the respective allocated portion of the predetermined train of instruction codes from the code storing means; a pair of decoding units (309a,309b) each for decoding instruction codes output from the corresponding output selecting unit; a pair of register units (310a,310b) each for storing instruction codes output from the corresponding output selecting unit; and a pair of instruction executing units (313a,313b) each for executing the respective instruction based on outputs of the corresponding decoding unit and register unit.

Claim 13

A data processor as set forth in claim 12, wherein the instruction storing means comprises: a memory means (126) for storing an instruction fed from the memory and a corresponding instruction length information obtained by the instruction length decoding means; and means (125) for reading a corresponding instruction and an instruction length information thereof from the memory means in the cache hit state and transmitting the read data to the control means, and for receiving a corresponding instruction from the memory and an instruction length information thereof from the instruction length decoding means in the cache miss state and writing the received data into the memory means.

Claim 14

A data processor as set forth in claim 13, further comprising means (123) for receiving a corresponding instruction from the memory and an instruction length information thereof from the instruction length decoding means in the cache miss state and transmitting the received data to the control means.

Claim 15

A data processor as set forth in claim 13, wherein the instruction length decoding means comprises: means (211∼214) for latching a variable length instruction data fed from the memory, with divided into a plurality of data blocks; means (221∼224, 231∼214) for decoding an instruction format and an effective address from the respective instruction data for every data block; means (241∼244) for determining respective instruction lengths based on the decoded results for every data block; means (250) for generating an instruction length information for the latched variable length instruction data based on the respective determined instruction lengths, and generating a control signal for indicating which block of the plurality of data blocks is at the head of the variable length instruction; and means (260), responsive to the control signal, for controlling the instruction length determining means to be enable or disable.

Claim 16

A cache memory (10a) for storing an instruction data (A) taken from a memory (30) and feeding the stored information to a control means (20), the cache memory comprising: means (14) for generating a predecoded information (B) as an auxiliary of a decoding of the instruction data; a memory means (15) for storing the predecoded information together with the instruction data; means (16) for checking a predecoded information output from the memory means together with a corresponding instruction data in the cache hit state; a rewriting means (17), where the checked predecoded information proves to be invalid or wrong, for rewriting the corresponding predecoded information in the memory means to a right one; and a control information outputting means (18,18a, 18b), where the checked predecoded information proves to be invalid or wrong, for outputting a control information reflecting a result of the check to the control means.

Claim 17

A cache memory as set forth in claim 16, wherein the control information outputting means comprises means (18), where the checked predecoded information proves to be invalid or wrong, for informing the control means of the invalidity of the predecoded information.

Claim 18

A cache memory as set forth in claim 16, wherein the control information outputting means comprises means (18a), where the checked predecoded information proves to be invalid or wrong, for outputting a re-predecoded information to the control means.

Claim 19

A cache memory as set forth in claim 16, wherein the control information outputting means comprises means (18b), where the checked predecoded information proves to be invalid or wrong, for rewriting the corresponding predecoded information to be fed to the control means to a right one.

Claim 20

A cache memory as set forth in claim 16, wherein the memory means comprises: a data memory (126a) for storing an instruction data fed from the memory and a corresponding predecoded information obtained by the predecoded information generating means; and means (125a) for reading a corresponding instruction data and a predecoded information thereof from the data memory in the cache hit state and transmitting the read data to the control means, and for receiving a corresponding instruction data from the memory and a predecoded information thereof from the predecoded information generating means in the cache miss state and writing the received data into the data memory.

Claim 21

A cache memory (10b) for storing an instruction data (A) taken from a memory (30) and feeding the stored information to a control means (20), the cache memory comprising: a memory means (15) for storing the instruction data together with a predecoded information (B) as an auxiliary of a decoding of the instruction data; means (19) for generating the predecoded information and checking a predecoded information output from the memory means together with a corresponding instruction data in the cache hit state; a rewriting means (17), where the checked predecoded information proves to be invalid or wrong, for rewriting the corresponding predecoded information in the memory means to a right one; and a control information outputting means (18,18a, 18b), where the checked predecoded information proves to be invalid or wrong, for outputting a control information reflecting a result of the check to the control means.

Claim 22

A data processor comprising: a processing means (20) for outputting an instruction address and fetching a variable length instruction; and a cache memory (10a,100a) connected between the processing means and a main memory, the cache memory including: means (14) for generating a predecoded information as an auxiliary of a decoding of the instruction data; a memory means (15) for storing the predecoded information together with the instruction data; means (16) for checking a predecoded information output from the memory means together with a corresponding instruction data in the cache hit state; a rewriting means (17), where the checked predecoded information proves to be invalid or wrong, for rewriting the corresponding predecoded information in the memory means to a right one; and a control information outputting means (18,18a,18b), where the checked predecoded information proves to be invalid or wrong, for outputting a control information reflecting a result of the check to the processing means.