EP0498107A2
Expired / Lapsed
EP
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A semiconductor memory device with an internal voltage generating circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1991-10-17
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Granted: —
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Expires: 2011-10-17
Abstract
Abstract A semiconductor memory device (600) receives an external control signal (K) repeatedly generated independently of an access to the memory device. The memory device includes an internal voltage generator (800; 900; 891;898) for generating a desired internal voltage in response to the control signal. The internal voltage generator includes a charge pump circuit (811; 830; 831; 920) responsive to the control signal. The internal voltage may provide a negative voltage such as a substrate bias voltage, or may be a positive voltage boosted over an operating power supply voltage and used as a boosted word line drive signal. This scheme eliminates an oscillator for generating a repeated clock signal to the charge pump circuit, leading to reduced current consumption and reduced chip area for the semiconductor memory device.
Inventors
- 👤 Masaki c/o Mitsubishi Denki Kumanoya
- 👤 Katsumi c/o Mitsubishi Denki Dosaka
- 👤 Yasuhiro c/o Mitsubishi Denki Konishi
- 👤 Akira c/o Mitsubishi Denki Yamazaki
- 👤 Hisashi c/o Mitsubishi Denki Iwamoto
- 👤 Kouji c/o Mitsubishi Denki Hayano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 17:41
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C8/00; G11C8/08; G11C11/005; G11C5/00; G11C5/14; G11C5/145; G11C5/146
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
65 words
A semiconductor memory device including a circuit portion (254; 250; 252; 897) which operates in response to an externally applied external control signal, said external control signal applied repeatedly no matter whether said semiconductor memory device is accessed or not, comprising: means (800; 900; 920; 891; 898) for generating an internal voltage used in said semiconductor memory device in response to said external control signal.
Claim 2
Dependent Claim
39 words
A semiconductor memory device according to claim 1, wherein said semiconductor memory device is formed on a semiconductor substrate, and wherein said means for generating includes means (800; 811) for applying a predetermined bias potential to said semiconductor substrate.
Claim 3
Dependent Claim
38 words
A semiconductor memory device according to claim 1, wherein said means for generating includes means (900; 920) responsive to said external control signal for generating a boosted signal having a level higher than an operating power supply potential.
Claim 4
Dependent Claim
37 words
A semiconductor memory device according to claim 3, further comprising means (91) responsive to a drive control signal for transmitting said boosted signal as a word line drive signal to be transferred onto a selected word line.
Claim 5
Dependent Claim
39 words
A semiconductor memory device according to claim 1, further comprising means (TQ90) responsive to a control signal (φz) for transmitting said internal voltage to an internal signal line to hold the internal signal line to said internal voltage level.
Claim 6
Dependent Claim
49 words
A semiconductor memory device formed on a single substrate, comprising: a clock input terminal for receiving a continuous external clock signal (KL; SC; CLK); and generating circuit means (800; 900; 891; 898) connected to said clock input terminal for generating an internal voltage in response to said clock signal.
Claim 7
Dependent Claim
22 words
A semiconductor memory device as recited in claim 6, wherein said internal voltage is a substrate bias voltage applied to said substrate.
Claim 8
Dependent Claim
22 words
A semiconductor memory device as recited in claim 6, wherein said generating circuit means comprises a charge pump circuit (811; 830; 831).
Claim 9
Dependent Claim
35 words
A semiconductor memory device as recited in claim 8, wherein said charge pump circuit comprises capacitor means (CP10; CP30) operable in response to said clock signal and clamping means (TQ50; TQ51; TQ52; TQ53; TQ60; TQ61).
Claim 10
Dependent Claim
19 words
A semiconductor memory device as recited in claim 9, wherein said clamping means comprises diode connected field effect transistors.
Claim 11
Dependent Claim
32 words
A semiconductor memory device as recited in claim 8, wherein said generating circuit means further comprises frequency divider circuit means (820) connected between said charge pump circuit and said clock input terminal.
Claim 12
Dependent Claim
27 words
A semiconductor memory device as recited in claim 11, wherein said frequency divider circuit means comprise a plurality of binary counter circuits (820) connected in cascade relationship.
Claim 13
Dependent Claim
58 words
A semiconductor memory device as recited in claim 8, further comprising a chip select terminal for receiving a signal (E) by which memory functions are enabled, and wherein said generating circuit means further comprises switching circuit means (835) connected to said chip select terminal for selectively activating said charge pump circuit in response to a chip select signal.
Claim 14
Dependent Claim
61 words
A semiconductor memory device as recited in claim 13, wherein said generating circuit means further comprises a second charge pump circuit (831) having different capability from a first charge pump circuit (830) and said switching circuit means comprises logic circuit means (AND1; AND2) for activating both said first and second charge means mutually exclusively in response to said chip select signal.
Claim 15
Dependent Claim
90 words
A semiconductor memory device as recited in claim 8, further comprising a chip select terminal for receiving a signal by which memory functions are enabled, and wherein said generating circuit means further comprises a pair of frequency divider circuit means (850; 851) having different division ratios connected to said charge pump circuit and to receive said clock input terminal; and switching circuit means (835) connected to said chip select terminal for activating both of said pair of frequency divider circuit means mutually exclusively in response to said chip select signal.
Claim 16
Dependent Claim
40 words
A semiconductor memory device as recited in claim 13, wherein said charge pump circuit comprises capacitor means (CP10; CP30) and diode connected field effect transistor switching means (TQ50; TQ51; TQ52; TQ53; TQ60; TQ61) operable in response to said clock signal.
Claim 17
Dependent Claim
32 words
A semiconductor memory device as recited in claim 15, wherein said charge pump circuit comprises capacitor means and diode connected field effect transistor switching means operable in response to said clock signal.
Claim 18
Dependent Claim
29 words
A semiconductor memory device as recited in claim 6, further comprising means (910) responsive to a control signal for transferring said internal voltage as an internal drive signal (φA).
Claim 19
Dependent Claim
29 words
A semiconductor memory device as recited in claim 18, wherein said internal voltage is at a level higher than an operating power supply voltage of said semiconductor memory device.
Claim 20
Dependent Claim
29 words
A semiconductor memory device as recited in claim 19, wherein said internal drive signal is a boosted word line drive signal to be transferred onto a selected word line.
Claim 21
Dependent Claim
102 words
A semiconductor memory device formed on a single semiconductor chip, comprising: a first memory array (1; 101; MH) including a plurality of dynamic type memory cells (DMC); a second memory array (2; 201; SMA) including a plurality of static type memory cells (SMC); data transfer means (3; BTG; 210) for transferring data between said first memory array and second memory array; control means (250; 252; 270) responsive to a repeatedly applied clock signal for generating internal signals for use in said semiconductor memory device; and voltage generating means (800; 900) responsive to said repeatedly applied clock signal for generating an internal voltage.
Claim 22
Dependent Claim
22 words
A semiconductor memory device according to claim 21, wherein said internal voltage provides a substrate bias voltage applied to said semiconductor chip.
Claim 23
Dependent Claim
28 words
A semiconductor memory device according to claim 21, wherein said internal voltage provides a boosted voltage higher than an operating power supply voltage of said semiconductor memory device.
Claim 24
Dependent Claim
36 words
A semiconductor memory device according to claim 23, further comprising transfer means (910) responsive to a transfer control signal (φZ) for transferring said internal voltage as an internal signal for use in said semiconductor memory device.
Claim 25
Dependent Claim
43 words
A semiconductor memory device according to claim 24, wherein said means for generating includes means (TQ90) for generating a boosted word line drive signal to be transferred onto a selected word line connecting a row of memory cells in said first memory array.
Claim 26
Dependent Claim
71 words
A semiconductor memory device according to claim 21, wherein said generating means includes charge pumping means (811; 830; 831) for generating said internal voltage through charge pumping operation of a capacitor means (CP10; CP30), and wherein said semiconductor memory device further includes means (835) responsive to a chip select signal (E) indicating enabling of said semiconductor memory device for controlling the charge pumping operation repeating cycle of said charge pumping means.
Claim 27
Independent Claim
38 words
A method of generating an internal voltage in a semiconductor device, comprising the steps of: in response to a clock signal repeatedly applied to said semiconductor memory device, generating said internal voltage for use in said semiconductor device.
Claim 28
Dependent Claim
40 words
The method according to claim 27, wherein said step of generating includes the step of generating, through charge pumping operation of a capacitor, a substrate bias voltage to be applied to a substrate where said semiconductor memory device is formed.
Claim 29
Dependent Claim
38 words
The method according to claim 27, wherein said step of generating includes the step of generating, through charge pumping operation of a capacitor, a boosted voltage signal higher than an operating power supply voltage of said semiconductor device.
Claim 30
Dependent Claim
62 words
The method according to claim 29, wherein said semiconductor device includes a plurality of dynamic type memory cells (DMC) arranged in a matrix of rows and columns, and wherein said step of generating includes the step of generating a boosted word line drive signal (φA) to be transferred onto a selected word line connecting a row of memory cells of said matrix.
Claim 31
Independent Claim
82 words
A method of generating an internal voltage for use in a semiconductor memory device comprising a cache memory (200) including a plurality of static type memory cells (SMC) and a main memory (100) including a plurality of dynamic type memory cells (DMC), and data transfer means (3; BTG; 210) for transferring data between said cache memory and said main memory, comprising the steps of: in a response to a clock signal repeatedly applied to said semiconductor memory device, generating said internal voltage.
Claim 32
Dependent Claim
42 words
The method according to claim 31, wherein said step of generating includes the step of generating, through charge pumping operation of a capacitor responsive to said clock signal, a bias voltage applied to a substrate wherein said semiconductor memory device is formed.
Claim 33
Dependent Claim
44 words
The method according to claim 31, wherein said step of generating includes the step of generating, through charge pumping operation of a capacitor responsive to said clock signal, a boosted voltage signal higher than an operating power supply voltage of said semiconductor memory device.
Claim 34
Dependent Claim
36 words
The method according to claim 33, further comprising the step of transferring said boosted voltage signal as an internal signal (φA) for use in said semiconductor memory device, in response to a transfer control signal (φZ).
Claim 35
Dependent Claim
60 words
The method according to claim 33, wherein said dynamic type memory cells are arranged in a matrix of rows and columns, and wherein said method further includes the step of transferring said boosted voltage signal onto a selected word line connecting a selected row of memory cells of said matrix, in response to a word line drive control signal (φZ).
References Cited (Backward Citations)
No citation records indexed.
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