EP0496506A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A processing unit for a computer and a computer system incorporating such a processing unit
Assignee: Hitachi Ltd
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Filing: 1992-01-10
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Granted: —
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Expires: 2012-01-10
Abstract
Abstract A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20- 2,20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2- 2,2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020- 1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.
Inventors
- 👤 Takeshi Miyao
- 👤 Manabu Araoka
- 👤 Tomoaki Nakamura
- 👤 Masayuki Tanji
- 👤 Shigenori Kaneko
- 👤 Koji Masui
- 👤 Saburou Iijima
- 👤 Shinichiro Yamaguchi
- 👤 Nobuyasu Kanekawa
- 👤 Yoshiki Kobayashi
- 👤 Hiroaki Fukumaru
- 👤 Katsunori Tagiri
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 22:42
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/187; G06F11/08; G06F11/10; G06F11/1008; G06F11/1064; G06F11/14; G06F11/1402; G06F11/1405; G06F11/141; G06F11/1604; G06F11/1666; G06F11/1675; G06F11/1679; G06F11/181; G06F11/183; G06F11/184; G06F11/20; G06F11/2002; G06F11/2007; G06F11/202; G06F11/2023; G06F11/2028; G06F11/203; G06F11/2035; G06F11/2043; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0833; G06F11/1629; G06F11/1641; G06F11/185; G11; G11C; G11C29/00; G11C29/70; G11C29/74
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
119 words
A processing unit (2-1,2-2,2-n) for a computer, comprising: a plurality of processors (20-1,20-2,20-3); and a common support board (PL), said plurality of processors (20-1,20-2,20-3) being supported by said common support board (PL); characterised in that: (i) a plurality of cache memories (220,221) are supported by said common support board and are respectively connected to at least one of said plurality of processors (20-1,20-2,20-3); and (ii) said plurality of processors (20-1,20-2,20-3) and said plurality of cache memories (220,221) are arranged to operate with redundancy among the respective pluralities of processors (20-1,20-2,20-3) and cache memories (220,221), whereby the processing unit remains operable despite a fault in any one of said plurality of processors (20-1,20-2,20-3) and said plurality of cache memories (220,221).
Claim 2
Dependent Claim
24 words
A processing unit according to claim 1, wherein the plurality of cache memories (220,221) are connected in common to the plurality of processors (20-1,20-2,20-3).
Claim 3
Dependent Claim
79 words
A processing unit according to claim 2 wherein each of said plurality of cache memories (220,221) is arranged to store data in common and said processing unit (2-1,2-2,2-n) further includes detection means (250) for detecting a fault in any one of said cache memories (220,221) after the detection of said fault; wherein said plurality of processors are arranged to access said data only in said plurality of cache memories (220,221) other than said any one of said cache memories.
Claim 4
Dependent Claim
23 words
A processing unit according to claim 1, wherein the plurality of cache memories (220,221) are respectively connected to different ones of said processors.
Claim 5
Dependent Claim
71 words
A processing unit according to any one of the preceding claims, further including a plurality of clocks (A,B) for generating clock pulses for controlling said plurality of processors (20-1,20- 2,20-3) said plurality of clocks (A,B) being supported by said common support board (PL), said plurality of clocks (A,B) being arranged to operate with redundancy therebetween, whereby the processing unit remains operable despite a fault in any one of said clocks (A,B).
Claim 6
Dependent Claim
111 words
A processing unit (2-1,2-2,2-n) for a computer, comprising: a plurality of processors (20-1,20-2,20-3) and a common support board (PL), said plurality of processors (20-1,20-2,20-3) are supported by said common support board; characterised in that: (i) a plurality of clocks (A,B) for generating clock pulses for controlling said plurality of processors are supported by said common circuit board (PL); and (ii) said plurality of processors (20-1,20-2,20- 3) and said plurality of clocks (A,B) are arranged to operate with redundancy among the respective pluralities of processors (20-1,20-2,20-3) and clocks (A,B), whereby the processing unit remains operable despite a fault in any one of said plurality of processors (20-1,20-2,20-3) and plurality of clocks (A,B).
Claim 7
Dependent Claim
112 words
A processing unit according to claim 5 or claim 6, wherein said plurality of clocks (A,B) includes at least first and second clocks, and said processing unit further includes means (1003) for comparing the duration of the clock pulses of said first and second clocks (A,B) and clock switching means (1004) for outputting said clock pulses of said first clock (A) when the duration of said clock pulses of said first and second clocks (A,B) have a relationship and for outputting the clock pulses of said second clock (B) when the duration of said clock pulses of said first and second clocks (A,B) have a second relationship different from said first relationship.
Claim 8
Dependent Claim
65 words
A processing unit according to any one of the preceding claims, wherein said plurality of processors (20-1,20-2,20-3) comprises at least three processors arranged to execute the same operation when operating without a fault, and the processing unit further includes detecting means (23-1,23-2,23-3) for detecting a fault in any one of said at least three processors (20-1,20-2,20-3) by comparison among said at least three processors (20-1,20-2,20-3).
Claim 9
Dependent Claim
89 words
A processing unit (2-1,2-2,2-n) for a computer, having: a plurality of processors (20-1,20-2,20-3) supported by a common support board (P1) said plurality of processors (20-1,20-2,20-3) being arranged to execute the same operation when operating without a fault; and a clock means (1000) on said common support board (PL) for controlling said at least three processors; characterised in that: the processing unit (2-1,2-2,2-n) has detecting means (23-1,23-2,23-3) for detecting a fault in any one of said at least three processors (20-1,20-2,20-3) by comparison among said at least three processors (20-1,20-2,20-3).
Claim 10
Dependent Claim
29 words
A processing unit according to claim 9 wherein said clock means comprises a plurality of clocks (A,B) for generating clock pulses for controlling said at least three processors (20-1,20-2,20-3).
Claim 11
Dependent Claim
99 words
A processing unit according to claim 10, wherein said plurality of clocks (A,B) includes at least first and second clocks, and said processing unit further includes means (1003) for comparing the duration of the clock pulses of said first and second clocks (A,B) and clock output switching means (1004) for outputting said clock pulses of said first clock (A) when the duration of said clock pulses of said first and second clocks (A,B) have a first relationship and for outputting the clock pulses of said first and second clocks (A,B) have a second relationship different from said first relationship.
Claim 12
Dependent Claim
30 words
A processing unit according to any one of claims 9 to 11 further including a plurality of cache memories (220,221) connected in common to said at least three processors (20-1,20-2,20-3).
Claim 13
Dependent Claim
79 words
A processing unit according to claim 12 wherein each of said plurality of cache memories (220,221) is arranged to store data in common and said processing unit further includes detection means (250) for detecting a fault in any one of said cache memories (220,221) after the detection of said fault; whereby said at least three processors (20-1,20-2,20-3) are arranged to access said data in said plurality of cache memories (220,221) other than said any one of said cache memories.
Claim 14
Dependent Claim
31 words
A processing unit according to any one of claims 7 to 9, further including a plurality of cache memories (220,221) respectively connected tp different ones of said at least three processors.
Claim 15
Dependent Claim
44 words
A processing unit according to any one of claims 8 to 14, wherein said detecting means (23-1,23-2,23-3) is arranged to prevent output from said any one of said at least three processors (20-1,20-2,20-3) on detection of said fault by said detection means (20- 1,20-2).
Claim 16
Dependent Claim
30 words
A processing unit according to any one of claims 8 to 15, having indication means (280) for generating an indication on detection of said fault by said detections means (23-1,23-2,23-3).
Claim 17
Dependent Claim
152 words
A processing unit (2-1,2-2,2-n) for a computer comprising: at least one processor (20-1,20-2,20-3) supported by a common support board (PL); first and second clocks (A,B) supported by said common support board (P,L) each of said first and second clocks (A,B) being for generating clock pulses; and means (1003) for comparing the duration of the clock pulses of said first and second clocks (A,B); characterised in that: the processing unit (2-1,2-2,2-n) has clock output switching means (1004) for outputting said clock pulses of said first clock (A) to said at least one processor (20-1,20-2,20-2) when the duration of said clock pulses of said first and second clocks (A,B) have a first relationship and for outputting the clock pulses of said second clock (B) to said at least one processor (20-1,20-2,20-3) when the duration of said clock pulses of said first and second clocks (A,B) have a second relationship different from said first relationship.
Claim 18
Dependent Claim
54 words
A processing unit according to claim 17, wherein said first relationship corresponds to equality of said duration of said clock pulses and said second relationships corresponds to the duration of any clock pulse of said pulses of said first clock (A) being longer than the duration of said pulses of said second clock (B).
Claim 19
Dependent Claim
122 words
A processing unit (2-1,2-2,2-n) having at least one processor (20-1,20-2,20-3) characterised in that: the processing unit (2-1,2-2,2-n) has a plurality of cache memories (220,221) connected in common to said at least one processor (20-1,20-2,20-3), and each arranged to store data in common; detection means (250) for detecting a fault in any one of said cache memories ( 20 - 1, 20- 2, 20-3 ) and for preventing access of said at least one processor to said any one of said cache memories ( 220, 2210 ) after the detection of said fault; whereby said at least one processor (20-1,20- 2,20-3) is arranged to access said data in said plurality of cache memories (220,221) other than said any one of said cache memories.
Claim 20
Dependent Claim
93 words
A processing unit (2-1,2-2,2-n) for a computer, comprising: a plurality of processors (20-1,20-2,20-3); and a common support board (PL), said plurality of processors (20-1,20-2,20-3) being supported by said common support board (PL); characterised in that: (i) there are at least four processors; and (ii) the processing unit has a detection means including first comparison means for comparing first and second ones of said at least four processors to detect a fault therein, and second comparison means for comparing third and fourth ones of said at least four processors to detect a fault therein.
Claim 21
Dependent Claim
30 words
A processing unit according to claim 16 or claim 17 wherein said processing unit also includes at least one clock (A,B) connected in common to said plurality of cache memories.
Claim 22
Dependent Claim
25 words
A processing unit according to any one of claims 19 to 21, wherein said detection means (250) includes parity check means for detecting said fault.
Claim 23
Dependent Claim
103 words
A processing unit (2-1,2-2,2-n) for a computer comprising: a processor (20-1,20-2,20-n); a first cache memory (2020-1,2020-2,2020-3) connected to said processor (20-1,20-2,20-3), said first cache memory (2020-1,2020-2,2020-3) being operable on the basis of n-set association, where n is an integer; and a second cache memory (220,221) connected to said first cache memory (2020-1,2020-2,2020-3), said second cache memory (220,221) being operable on the basis of m-set association, where m is an integer less than n; characterised in that: the processing unit 2-1,2-2,2-n) has means for generating an invalidity signal to said first cache memory (2020-1,2020-2,2020-3) when data in said second cache memory (220,221) is changed.
Claim 24
Dependent Claim
110 words
A processing unit (2-1,2-2,2-3) for a computer, comprising: a processor (20-1,20-2,20-3) a first cache memory (2020-1,2020-2,2020-3) connected to said processor (20-1,20-2,20-3) said first cache memory (2020-1,2020-2,2020-3) being operable on the basis of n-set association, where n is an integer; and a second cache memory (220,221) connected to said first cache memory (2020-1,2020-2,2020-3), said second cache memory (220,221) being operable on the basis of m-set association, where m is an integer less than n; characterised in that: the processing unit (2-1,2-2,2-n) has means for controlling said first (2020-1,2020-2,2020-3) and second (220,221) cache memories such that all data in said first cache memory (2020-1,2020-2,2020-3) is also in said second cache memory (220,221).
Claim 25
Dependent Claim
114 words
A processing unit (2-1,2-2,2-n) for a computer comprising: a processor (20-1,20-2,20-3); a first cache memory (2020-1,2020-2,2020-3) connected to said processor (20-1,20-2,20-3) said first cache memory (2020-1,2020-2,2020-3) being operable on the basis of n-set association, where n is an integer; and a second cache memory (220,221) connected to said first cache memory (2020-1,2020-2,2020-3) said cache memory (220,221) being operable on the basis of m-set association where m is an integer less than n; characterised in that: the processing unit (2-1,2-2, 2-n) has means for controlling said first (2020-1,2020-2,2020-3) and second cache memories (220,221) such that only said data in said second cache memory (220,221) is permitted to remain in said first cache memory (2020- 1,2020-2,2020-3).
Claim 26
Dependent Claim
46 words
A processing unit according to any one of claims 23 to 25, wherein said first cache memory (2020- 1,2020-2,2020-3) also stores said data, and said invalidity signal is such as to prevent access by said processor (20-1,20-2,20-3) to said data in said first cache memory (2020-1,2020-2,2020-n).
Claim 27
Dependent Claim
28 words
A processing unit according to any one of claims 23 to 26 wherein said processor (20-1,20-2,20-3) and said first cache memory (2020-1,2020-2,2020-3) are integral in a common component.
Claim 28
Dependent Claim
17 words
A computer system including a plurality of processing units according to any one of the preceding claims.
Claim 29
Dependent Claim
29 words
A computer system according to claim 28 wherein each of said common support boards (PL) of said plurality of processing units (2-1,2-2,2-n) is removably mounted in a mounting rack.
Claim 30
Dependent Claim
70 words
A computer system according to claim 28 or claim 29, further including at least one system bus (1-1,1-2) and a main memory (3-1,3-2) connected to said at least one system bus (1-1,1-2), each of said processing units (2-1, 2-2,2-n) being operatively connected to said at least one system bus (1-1,1-2) for communication between said main memory (3-1,3-2) and said processors(s) (20-1,20-2,20-3) of each of said plurality of processing units (2-1,2-2,2-n).
Claim 31
Dependent Claim
105 words
A computer system having: first and second clocks (A,B) each for generating clock pulses; and means (1003) for comparing the duration of the clock pulses of said first and second clocks (A,B); characterised in that: the computer system has clock output switching means (1004) for outputting said clock pulses of said first clock (A) when the duration of said clock pulses of said first and second clocks (A,B) have a first relationship and for outputting the clock pulses of said second clock (B) when the duration of said clock pulses of said first and second clocks(A,B) have a second relationship different from said first relationship.
Claim 32
Dependent Claim
54 words
A computer system according to claim 31, wherein said first relationship corresponds to equality of said duration of said clock pulses and said second relationship corresponds to the duration of any clock pulse of said pulses of said first clock (A) being longer than the duration of said pulses of said second clock (B).
Claim 33
Dependent Claim
34 words
A computer system according to claim 31 or claim 32 further including at least one processor (20-1,20-2,20-3) said first and second clocks (A,B) being connected in common to said at least one processor (20-1,20-2,20-3).
Claim 34
Dependent Claim
16 words
A method according to claim 33, further including generating an indication when said fault is detected.
Claim 35
Independent Claim
151 words
A method of operating a computer having a plurality of processing units (2-1,2-2,2-n), each said processing unit (2-1,2-2,2-n) having a plurality of processors supported by a common support board (PL), said plurality of processors being arranged to execute the same operation; said method comprising: causing a first one of said processing units (2- 1,2-2,2-n) to execute said operations in each of the processors (20-1,20-2,20-3) thereof; detecting a fault in said plurality of processors (20-1,20-2,20-3) of said first one of said processing units (2-1,2-2,2-n); causing said execution of said operation to be transferred to a second one of said processing units (2-1,2-2,2-n) for execution in each of the processors (20-1,20-2,20-3) thereof; and ceasing execution of said operation in each of said plurality processors (20-1,20-2,20-3) of said first one of said processing units (2-1,2-2,2-n); characterised in that: the plurality of processors (20-1,20-2,20-3) comprise at least three processors having a common clock unit (1000).
Claim 36
Dependent Claim
91 words
A method according to claim 35, wherein after detection of said fault but prior to transfer of said operation; the one of said at least three processors (20- 1,20-2,20-3) in which said fault occurs is identified; said one of said at least three processors (20- 1,20-2,20-3) is caused to cease execution of said operation; and said execution of said operation is continued in said at least three processing units (20-1,20-2,20-3) of said first one of said processing units other than said any one of said at least three processing units (20-1,20-2,20-3).
Claim 37
Independent Claim
168 words
A method of operating a computer system having a plurality of processing units (2-1,2-2,2-n) and a main memory (3-1,3-2), each processing unit (2-1,2-2,2-n) comprising at least one processor (20-1,20-2,20-3) and at least one cache memory (220,221); said method comprising: storing data in common in said main memory (3- 1,3-2) and said at least one cache memory of each of said processing units; and causing said at least one processor (20-1,20- 2,20-3) of a first one of said processing units (2- 1,2-2,2-3) to access said data in said main memory (3- 1,3-2); characterised in that: an invalidity signal is generated to said at least one cache memory of each of said processing units (2-1,2-2,2-n) other than said first processing unit, which invalidity signal prevents access of said at least one processor (20-1,20-2,20-3) of each of said processing units (2-1,2-2,2-n) other than said first processing unit to said data in said at least one cache memory (220,221) of each of said processing units (20-1,20-2,20-3) other than said first processing unit.
Claim 38
Independent Claim
158 words
A method of operating a processing unit for a computer; said processing unit having: a common support board; at least four processors supported by said support board, said at least four processors being arranged to execute the same operation when operating without a fault; a clock means on said common support board for controlling said at least four processors; and detecting means having first comparison means for comparing first and second ones of said at last four processors to detect a fault therein, and second comparison means for comparing third and fourth ones of said at least four processors; said method comprising: detecting a fault in said first and second ones of said at least four processors by said first comparison means; causing said first and second ones of said at least four processors to cease execution of said operation; and continuing execution of said operation in said third and fourth ones of said at least four processors.
References Cited (Backward Citations)
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