EP0495650A2
Expired / Lapsed
EP
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Method of fabricating field-effect transistor
Assignee: Sharp Corp
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Filing: 1992-01-16
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Granted: —
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Expires: 2012-01-16
Abstract
Abstract A method of fabricating an insulating gate type field-effect transistor in which a region (4) having a low carrier density for mitigating electric field is provided so as to abut on a source/drain region (6) having a high carrier density, the method comprising the steps of: forming a gate insulating film (2) and a gate electrode (3) on a semiconductor substrate (1); depositing an insulating thin film (5) on the gate electrode (3) and the gate insulating film (2) to a vertical thickness (t1); and performing from above the insulating thin film (5), ion implantation at an implantation energy inducing a projected range of ions approximately equal to the vertical thickness (t1) of the insulating thin film (5) so as to form the source/drain region (6); wherein a horizontal thickness (t2) of the insulating thin film (5) on opposite sides of the gate electrode (3) is larger than a sum of a lateral diffusion distance (ΔRt) of the source/drain region (6) at the time of the ion implantation and a lateral diffusion distance (D) of the source/drain region (6) after the ion implantation.
Inventors
- 👤 Seizo Kakimoto
- 👤 Katsuji Iguchi
- 👤 Sung Tae Ahn
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 20:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10P; H10P30/00; H10P30/20; H10P30/222
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
183 words
A method of fabricating an insulating gate type field-effect transistor in which a region (4) having a low carrier density for mitigating electric field is provided so as to abut on a source/drain region (6) having a high carrier density, the method comprising the steps of: forming a gate insulating film (2) and a gate electrode (3) on a semiconductor substrate (1); depositing an insulating thin film (5) on the gate electrode (3) and the gate insulating film (2) to a vertical thickness (t1); and performing from above the insulating thin film (5), ion implantation at an implantation energy inducing a projected range of ions approximately equal to the vertical thickness (t1) of the insulating thin film (5) so as to form the source/drain region (6); wherein a horizontal thickness (t2) of the insulating thin film (5) on opposite sides of the gate electrode (3) is larger than a sum of a lateral diffusion distance (ΔRt) of the source/drain region (6) at the time of the ion implantation and a lateral diffusion distance (D) of the source/drain region (6) after the ion implantation.
Claim 2
Dependent Claim
31 words
A method as claimed in Claim 1, wherein the vertical thickness (t1) of the insulating thin film (5) is equal to the horizontal thickness (t2) of the insulating thin film (5).
Claim 3
Independent Claim
244 words
A method of fabricating an insulating gate type field-effect transistor in which a region (4) having a low carrier density for mitigating electric field is provided so as to abut on a source/drain region (6) having a high carrier density, the method comprising the steps of: forming a gate insulating film (2) and a gate electrode (3) on a silicon substrate (1) sequentially; performing, by using the gate electrode (3) as a mask, ion implantation not only at an acceleration energy inducing a larger projected range of ions than a thickness of the gate insulating film (2) but at a dose sufficiently smaller than a predetermined dose for forming the source/drain region (6) so as to form the region (4) in the silicon substrate (1); depositing an insulating thin film (5) on the gate electrode (3) and the gate insulating film (2) to a vertical thickness (t1); performing further ion implantation at an implantation energy inducing a projected range of ions approximately equal to the vertical thickness (t1) of the insulating thin film (5) so as to form the source/drain region (6); and performing heat treatment; wherein a horizontal thickness (t2) of the insulating thin film (5) on opposite sides of the gate electrode (3) is larger than a sum of a lateral diffusion distance (ΔRt) of the source/drain region (6) at the time of the further ion implantation and a lateral diffusion distance (D) of the source/drain region (6) after the heat treatment.
Claim 4
Independent Claim
264 words
A method of fabricating a semiconductor device, comprising the steps of: forming on a substrate (51) having a gate electrode (54), a stack of a lower silicon dioxide film (55), an etching stopper film (56) made of a material capable of being etched selectively for a silicon dioxide film and an upper silicon dioxide film (57) so as to set the stack of the lower silicon dioxide film (55), the etching stopper film (56) and the upper silicon dioxide film (57) to a predetermined thickness such that an upper face and opposite side faces of the gate electrode (54) and a portion of a surface of the substrate (51) disposed on opposite sides of the gate electrode (54) are covered by the stack; performing ion implantation substantially perpendicularly to the surface of the substrate (51) through the stack such that a pair of n⁺ type regions (59) or a pair of p⁺ type regions (60) acting as source and drain regions are, respectively, formed at locations which are disposed on opposite sides of the gate electrode (54) and are spaced a distance approximately equal to the thickness of the stack from the gate electrode (54); etching the upper silicon dioxide film (57) up to the etching stopper film (56); and performing further ion implantation substantially perpendicularly to or obliquely relative to the surface of the substrate (51) so as to form an n⁻ type region (61) or a p⁻ type region (62) at an end portion of the n⁺ type regions (59) or the p⁺ type regions (60) adjacent to the gate electrode (54).
Claim 5
Dependent Claim
69 words
A method as claimed in claim 4, further comprising the step of performing ion implantation obliquely relative to the surface of the substrate (51) so as to form a halo region (63) having a conductive type opposite to that of the n⁻ type region (61) or the p⁻ type region (62) such that the halo region (63) encloses the n⁻ type region (61) or the p⁻ type region (62).
Claim 6
Independent Claim
204 words
A method of fabricating a semiconductor device, comprising the steps of: forming on a substrate (51) having a gate electrode (54), a stack comprising at least two layers (55, 56, 57), the stack having a predetermined thickness and covering an upper face and opposite side faces of the gate electrode (54) and a portion of a surface of the substrate (51) disposed on opposite sides of the gate electrode (54); performing ion implantation substantially perpendicularly to the surface of the substrate (51) through the stack such that two n⁺ type regions (59) or two p⁺ type regions (60), acting as source and drain regions, are, respectively, formed on opposite sides of the gate electrode (54) and are spaced a distance approximately equal to the thickness of the stack from the gate electrode (54); reducing the thickness of the stack by removing an outer layer (57) thereof; and performing further ion implantation substantially perpendicularly to or obliquely relative to the surface of the substrate (51) through the reduced-thickness stack so as to form an n⁻ type region (61) or a p⁻ type region (62) at end portions of the n⁺ type regions (59) or the p⁺ type regions (60) adjacent to the gate electrode (54).
Claim 7
Dependent Claim
73 words
A method as claimed in claim 6, further comprising the step of performing ion implantation obliquely relative to the surface of the substrate (51) through the reduced-thickness stack so as to form a halo region (63) having a conductive type opposite to that of the n⁻ type region (61) or the p⁻ the region (62) such that the halo region (63) encloses the n⁻ type region (61) or the p⁻ type region (62).
Claim 8
Independent Claim
72 words
A method for fabricating an insulated-gate type semiconductor device in which a region having a low carrier density abuts, in the vicinity of the gate, a source/drain region having a high carrier density, characterised in that the high carrier density region is formed before the low carrier density region is formed so that heat treatment of the high carrier density region can be performed before the low carrier density region is formed.
References Cited (Backward Citations)
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