EP0495572A2
Expired / Lapsed
EP
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Refreshing ferroelectric capacitors
Assignee: National Semiconductor Corp
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Filing: 1992-01-07
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Granted: —
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Expires: 2012-01-07
Abstract
Abstract The invention relates in general to refreshing of ferroelectric capacitors. In one aspect, the invention relates to methods and apparatus for refreshing memory arrays having ferroelectric capacitors cells to increase the long-term endurance thereof. In order to refresh the ferroelectric material a voltage greater than the normal operational voltage across the capacitor is applied.
Inventors
- 👤 Reza N.M.I. Moazzami
- 👤 James M. Jaffee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 22:53
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G11C11/34; G11C11/40; G11C11/223
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
29 words
A method for extending the endurance of a ferroelectric capacitor (12) comprising applying a voltage greater than the normal operational voltage across the capacitor to refresh the ferroelectric material.
Claim 2
Dependent Claim
97 words
A method according to claim 1 further comprising applying voltages to charge and discharge the ferroelectric capacitor (12) during a normal operational period of a circuit with which the capacitor is associated, said voltages not exceeding a predefined operational voltage, and causing the storage of useful information within said ferroelectric capacitor, and applying a refresh signal voltage one or more times across the capacitor (12) which is greater in magnitude than the predefined voltage applied to the capacitor during the normal operational period, said refresh signal voltage being effective to revitalize the ferroelectric material of the capacitor.
Claim 3
Dependent Claim
21 words
A method according to claim 1 or claim 2 further including applying a digital refresh signal voltage across the ferroelectric capacitor.
Claim 4
Independent Claim
19 words
A method according to any preceding claim, further including applying the refresh signal voltage during a normal operational period.
Claim 5
Independent Claim
28 words
A method according to any preceding claim, further including applying the refresh signal voltage across the ferroelectric capacitor to re-establish a desired polarization state stored by the capacitor.
Claim 6
Independent Claim
70 words
A method according to any preceding claim in which the ferroelectric capacitor is part of a memory cell (40, 42, 44), further comprising a word line (16), a bit line (20) and a drive line (18) in which the memory cell is accessed by addressing the word line and the operational voltage is applied across the ferroelectric capacitor to read or write the cell with respect to a polarization state.
Claim 7
Independent Claim
74 words
A method according to any preceding claim in which the ferroelectric capacitor is part of a cell (40, 42, 44) which is itself part of an addressable memory array and the cells of the array are periodically refreshed by sequentially applying an address to a word line (16) associated with the cell and applying the higher than normal operating voltage across the ferroelectric capacitor via a drive line (18) and a bit line (20).
Claim 8
Dependent Claim
29 words
A method according to claim 6 or claim 7, further including increasing the drive line (18) voltage and maintaining the bit line (20) voltage substantially constant during the refresh.
Claim 9
Independent Claim
48 words
A method according to any of claims 6 to 8, further including maintaining the drive line (18) with a predefined drive line voltage and increasing the bit line voltage so that the potential impressed across the ferroelectric capacitor corresponds to said voltage greater than the normal operating voltage.
Claim 10
Independent Claim
49 words
A method according to any preceding claim, further including counting the number of memory access cycles to which the capacitor has been subjected, and on a predefined count, initiating said refresh operation and/or waiting a predefined period of time after one refresh operation before initiating a subsequent refresh operation.
Claim 11
Dependent Claim
34 words
A method according to claim 10, further including waiting decreasing or nonuniform periods of time between said refresh operations and/or refreshing the capacitor with increased magnitudes of refresh voltage at each subsequent refresh operation.
Claim 12
Independent Claim
33 words
A method according to any preceding claim, wherein a semiconductor chip includes an array of ferroelectric capacitors and wherein said refresh operation is carried out by increasing a supply voltage to said chip.
Claim 13
Independent Claim
33 words
A method according to any preceding claim, further including during each refresh operation, subjecting the ferroelectric capacitor to a plurality of pulses, each of which has a magnitude corresponding to said second magnitude.
Claim 14
Independent Claim
43 words
A method according to any preceding claim, further including carrying out a refresh sequence by reading and temporarily storing data associated with the capacitor in a sense amplifier (22), refreshing the memory capacitor, and rewriting the temporarily stored data back into the capacitor.
Claim 15
Independent Claim
57 words
A method according to any preceding claim, further including increasing the voltage across the ferroelectric capacitor to V cc or a magnitude of about 50% greater than the magnitude normally impressed across the capacitor during a read cycle or V cc /2, preferably applying 2-3 volts across the capacitor for reading and approximately 5 volts for refreshing.
Claim 16
Independent Claim
37 words
A method according to any preceding claim, in which the capacitor is part of an array of such capacitors that includes rows and columns and further including sequentially refreshing each row during a respective single refresh operation.
Claim 17
Dependent Claim
92 words
A ferroelectric memory array, comprising an array of memory cells, each cell including a ferroelectric capacitive element, circuits for accessing the array to address a desired memory cell, a voltage drive circuit (34) for applying a voltage of a first magnitude across the ferroelectric capacitor of the addressed cell during a normal memory read/write operation, and means (30) for applying a second voltage of a magnitude greater than said first magnitude across the capacitive element of each addressed cell during a fresh operation to refresh the ferroelectric material of the capacitive elements.
Claim 18
Dependent Claim
36 words
The memory array of claim 17, further including a circuit for driving the capacitive element with the second voltage to refresh the material of the capacitor during a refresh operation subsequent to a memory read operation.
Claim 19
Dependent Claim
81 words
A memory array according to claims 17 or 18, further including a common drive line circuit for applying a voltage to a number of ferroelectric capacitors of respective cells connected to the common drive line, and a circuit associated with said drive line circuit for driving the drive line with a voltage of a first magnitude for read operations, and for driving the drive line with a voltage of a second magnitude greater than the first magnitude during a refresh operation.
Claim 20
Dependent Claim
64 words
A memory array according to any of claims 17 to 19, further including a sense amplifier (22) associated with a bit line to which said memory cells are connected, said sense amplifier having a voltage drive circuit for driving said bit line with a first voltage during normal rewrite operations, and for driving the bit line with a higher voltage during a refresh operation.
Claim 21
Dependent Claim
26 words
A memory array according to any of claims 17 to 20, further including a drive circuit for applying a refresh voltage directly across each ferroelectric capacitor.
Claim 22
Dependent Claim
27 words
A memory array according to any of claims 17 to 21, wherein said drive circuit is connected across a common drive line and a common bit line.
Claim 23
Dependent Claim
110 words
A ferroelectric memory array, comprising an array of memory cells, each cell including a ferroelectric capacitive element, circuits for accessing the array to address a desired memory cell, a bit line common to a number of memory cells for transferring electric charge to and from the ferroelectric capacitive elements of addressed cells, a drive line common to a number of memory cells for applying a drive voltage to ferroelectric capacitive elements, and a drive circuit connected to said bit line and to said drive line for applying a refresh voltage directly across the ferroelectric capacitive element of at least one cell associated with the drive line and the bit line.
Claim 24
Dependent Claim
67 words
A ferroelectric memory array according to claim 23, wherein during a normal cell access the cell is configured to distribute electric charge between the ferroelectric capacitive element and capacitance of the bit line so that the resultant voltage across the ferroelectric capacitive element is always less than V, and during a refresh operation a voltage of V is applied across the drive line and the bit line.
Claim 25
Dependent Claim
31 words
A ferroelectric memory array according to claims 23 or 24, further including an oscillator for applying a plurality of refresh voltage pulses to the ferroelectric capacitive element during a refresh operation.
Claim 26
Dependent Claim
109 words
A ferroelectric memory, comprising a plurality of memory cells (40, 42, 44) each having a ferroelectric capacitive element (12), at least one bit line (20) connected to at least one said cell, at least one drive line (18) connected to at least one said cell, a sense amplifier, an isolation transistor for switchably connecting said bit line (20) to said sense amplifier during reading of the cell, and for isolating the bit line from the sense amplifier during refreshing of the cell, and a drive circuit operative during refreshing of the cells for applying a voltage between the drive line and the bit line to refresh the capacitive elements.
Claim 27
Dependent Claim
17 words
A memory according to claim 26, further including an oscillator (148) for driving the drive line circuit.
Claim 28
Dependent Claim
30 words
A memory according to any of claims 17 to 27, further including a counter (140) for totalizing memory accesses, and for initiating a refresh after a predetermined number of accesses.
Claim 29
Dependent Claim
40 words
A memory according to any of claims 17 to 27, wherein said drive circuit (78) includes a first CMOS transistor pair (86, 88) connected to the drive line and a second CMOS pair (80, 82) connected to the bit line.
Claim 30
Dependent Claim
22 words
A memory according to claim 29, wherein each said CMOS transistor pair is connected in series between supply voltages of said memory.
Claim 31
Dependent Claim
22 words
A memory according to any of claims 17 to 30, wherein said counter is formed on a semiconductor chip with said array.
Claim 32
Dependent Claim
18 words
A memory according to any of claims 17 to 31, wherein said counter has stages which are nonvolatile.
Claim 33
Dependent Claim
31 words
A memory according to any of claims 17 to 32 or claim 32, wherein said memory array is formed on a silicon chip, and said counter is located off said chip.
Claim 34
Dependent Claim
40 words
A memory according to any of claims 17 to 33, wherein said array is formed on a semiconductor chip supplied with a supply voltage defined as V cc , and means for increasing the supply voltage during a refresh operation.
Claim 35
Dependent Claim
33 words
A memory array according to claim 29, further including an inverter (96) for inverting a drive signal before being applied to one of said CMOS transistor pairs to provide out of phase signals.
Claim 36
Independent Claim
68 words
A method of refreshing cells of a ferroelectric memory chip, comprising the steps of increasing a supply voltage connected to a pin of said chip from a first magnitude from which the chip normally operates in read and write operations to a greater magnitude, and accessing each cell of the array with said increased magnitude voltage applied to the chip to refresh the ferroelectric material of each cell.
Claim 37
Dependent Claim
18 words
A method according to claim 36, wherein said accessing step is carried out by reading each memory cell.
Claim 38
Dependent Claim
23 words
A method according to claim 36, wherein said supply voltage is increased by increasing either a positive supply voltage or a negative supply.
References Cited (Backward Citations)
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