EP0495165A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Overlapped serialization
Assignee: International Business Machines Corp
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Filing: 1991-11-06
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Granted: —
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Expires: 2011-11-06
Abstract
Abstract A system and method whereby a central processor can continue operation beyond a serialization point before the architecture defines that it is permissible to do so. According to the system and method, it is ascertained whether correct results are being achieved after the serializing point. If some doubt develops about the correctness of the results, the processor is returned to its status at the serialization point and the processing is repeated. In one embodiment, correctness of results is determined by way of a monitoring mechanism which depends on the fact that the interactions between CPUs are confined to references to storage. The operations which are performed prior to the time that the architecture allows them, are restricted to ones which depend on fetches made from storage. The needed assurance of correct operation is gained by monitoring the storage locations from which fetches are made on behalf of instructions which logically follow the serializing operation, but which are made prior to the time that fetching is allowed to resume. If those storage locations are not changed during the time between when the first such fetch is actually made from one of them, and the time that fetching is allowed to resume, then the results of the processing which was done by the CPU (based on those fetches) must be exactly the same as if all of the fetches and all of the processing was done in a single instant at the moment that the fetches became allowed.
Inventors
- 👤 Steven Tyler Comfort
- 👤 John Stephen Liptay
- 👤 Charles Franklin Webb
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 12:24
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3861
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
150 words
An apparatus for processing instructions beyond a serializing point, comprising: a central processing unit; a memory coupled to the central processing unit, the memory comprising a cache memory system; fetching means, coupled to the memory, for fetching instructions from the memory; monitoring means for determining the validity of data in the cache memory system; decoding means, coupled to the fetching means, for decoding the instructions, the decoding means comprising detection means for detecting decoding of a serializing instruction; and, conditional path means, coupled to the monitoring means and the decoding means, for resetting the central processing unit to conditions existing just prior to decoding of an instruction immediately following the serializing instruction, when the monitoring means indicates that at least a subset of the data in the cache memory system is not valid, the conditional path means being enabled responsive to decoding of the serializing instruction by the decoding means.
Claim 2
Dependent Claim
31 words
The apparatus of Claim 1, wherein said decoding means further comprises: inhibit means for inhibiting decoding of further serializing instructions when the detection means detects decoding of a first serializing instruction.
Claim 3
Dependent Claim
88 words
The apparatus of Claim 2, further comprising: fetch queue means, coupled to said decoding means, for queuing data fetch requests to said memory; sequencing means, coupled to the fetch queue means, for causing data fetch requests associated with instructions prior to the first serializing instruction to be performed prior to data fetch requests associated with the first serializing instruction, and for causing the data fetch requests associated with the first serializing instruction to be performed prior to data fetch requests associated with instructions subsequent to the serializing instruction.
Claim 4
Dependent Claim
35 words
The apparatus of Claim 3 wherein the cache memory system includes an instruction cache, and wherein the monitoring means includes means for monitoring whether a line of data has been removed from the instruction cache.
Claim 5
Dependent Claim
41 words
The apparatus of Claim 3, further comprising indicator means, coupled to the fetching means and the monitoring means, for storing an indicator bit indicative of whether at least a subset of the data in the cache memory system is not valid.
Claim 6
Dependent Claim
121 words
The apparatus of Claim 5, wherein the conditional path means comprises: a first table for storing assignments of a subset of physical registers in the central processing unit to perform functions for a set of architected logical registers, a second table coupled to the first table, first means, coupled to the decoding means, for copying the assignments from the first table to the second table responsive to decoding of the serializing instruction by the decoding means; second means, coupled to the monitoring means, for copying the assignments from the second table back to the first table responsive to a determination by the monitoring means that the at least a subset of the data in the cache memory system is not valid.
Claim 7
Independent Claim
99 words
An apparatus for enabling a central processor to process instructions beyond a serializing point, comprising: monitoring means for monitoring validity of data in a cache memory coupled to the central processor; conditional path means, coupled to the monitoring means, for restoring the central processor to conditions existing just after the serializing point, when the monitoring means indicates that at least a subset of the data in the cache memory is not valid; and, serializing means, coupled to the conditional path means, for enabling the conditional path means in response to decoding of a serializing instruction by the central processor.
Claim 8
Dependent Claim
20 words
The apparatus of Claim 7, further comprising: means for commencing execution of a stream of instructions following the serializing instruction.
Claim 9
Independent Claim
74 words
An apparatus for processing instructions beyond a serializing point, comprising: fetching means for fetching a plurality instructions; decoding means, coupled to the fetching means, for decoding the instructions, the decoding means comprising means for detecting presence of a serializing instruction amongst the plurality of instructions; conditional execution means, coupled to the decoding means, for conditionally executing at least one instruction following the serializing instruction in the plurality of instructions fetched by the fetching means.
Claim 10
Dependent Claim
49 words
The apparatus of Claim 9, further comprising, monitoring means for determining validity of data in a cache memory of a computer system, wherein the conditional execution means further comprises means for causing the computer system to perform a pipeline reset, in response to a signal from the monitoring means.
Claim 11
Independent Claim
109 words
A method for processing serializing instructions, comprising: a monitoring step of continuously monitoring validity of data in a cache memory of a central processor; a decoding step of decoding a serializing instruction; a status storing step of storing data indicative of a state of the central processor, responsive to decoding of the serializing instruction; a fetching step of fetching at least one instruction following the serializing instruction; and a status restoring step of, after the fetching step, restoring the central processor to conditions existing just after the decoding step, when the monitoring step indicates that at least a subset of the data in the cache memory is not valid.
Claim 12
Dependent Claim
22 words
The method of Claim 11, further comprising the step of commencing execution of the at least one instruction following the serializing instruction.
Claim 13
Dependent Claim
24 words
The method of Claim 12, wherein the monitoring step comprises a step of monitoring the cache memory system for removal of a line therefrom.
Claim 14
Dependent Claim
25 words
The method of Claim 13, further comprising the step of setting a bit corresponding to the at least one instructions fetched by the fetching step.
Claim 15
Dependent Claim
84 words
The method of Claim 14, wherein the decoding step further comprises the step of storing, in a first table, data indicative of assignment of physical registers in the central processor, to receive data for logical registers architected in the central processor; wherein the status storing step comprises the step of copy the first data from the first table to a second table; and, wherein the restoring step comprises the step of copying the assignment data back from the second table into the first table.
References Cited (Backward Citations)
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