Liquid crystal display

Claim 2

Halftone grayscale liquid crystal display comprising a plurality of pixels having high pixel aperture ratio, wherein each pixel comprises: a first substrate (88); a N number of subpixels (71,72,73,74,75,76) wherein each of N-1 subpixels comprises: a first electrode (81) on said first substrate; a layer of dielectric (78) on said first electrode; a second electrode (82) on said layer of dielectric; a layer of liquid crystal (112) on said second electrode; and a third electrode (114) on said layer of liquid crystall; and wherein the Nth subpixel (72) comprises: a first electrode (81) on said first substrate (88); a layer of dielectric (78) on said first electrode (81); a layer of liquid crystal (112) on said layer of dielectric (78); and a second substrate electrode (114) on said layer of liquid crystel (112); and wherein said first electrodes (81) of the N-1 subpixels are interconnected.

Claim 3

Display according to claim 2, characterized in that said each of N-1 subpixels (71,73,74,75,76) are proximate to one another; said Nth subpixel (72) is situated between said N-1 subpixels; and said first electrodes (81) of at least one of said N-1 subpixels and of said Nth subpixel are interconnected.

Claim 4

Display according to claim 2, characterized in that said each of N-1 subpixels (91,93) are concentric to one another and to said Nth subpixel (92).

Claim 5

Display according to claim 2 further characterized by a coupling capacitor (106) wherein said coupling capacitor comprises: a first electrode connected to said first electrode of at least one of said each of N-1 subpixels (102,103); and a second electrode capacitively connected to said first electrode of said Nth subpixel (101).

Claim 6

Halftone grayscale liquid crystal display comprising a plurality of pixels having a high pixel aperture ratio, wherein each pixel comprises: first (42), second (43), third (44), fourth (45) and fifth (41) subpixels; a first glass substrate (88); a first electrode (62) on said glass substrate; a second electrode (63) on said glass substrate; a third electrode (64) on said glass substrate; a fourth electrode (65) on said glass substrate; a fifth electrode (51) situated between said first, second, third and fourth electrodes, respectively, on said glass substrate (88) and proximate to said fifth subpixel; a dielectric layer on said at least first (42), second (43), third (44) and fourth (45) electrodes; a sixth electrode (52) situated on said dielectric layer proximate to said first electrode (62) and said first subpixel (42); a seventh electrode (53) situated on said dielectric layer proximate to said second electrode (63) and said second subpixel (43); an eighth electrode (54) situated on said dielectric layer proximate to said third electrode (64) and said third subpixel (44); a ninth electrode (55) situated on said dielectric layer proximate to said fourth electrode (65) and said fourth subpixel (45); a liquid crystal layer (112) situated on said fifth (51), sixth (52), seventh (53), eighth (54) and ninth (55) electrodes; a tenth electrode on said liquid crystal (114); and a second glass substrate (114) on said tenth electrode.

Claim 7

Display according to claim 6, characterized in that said first, second, third, fourth and fifth electrodes (62-65,51) are connected to one another.

Claim 8

Display according to claim 7 further characterized by a transistor (TFT,60) connected to at least one of said first, second, third, fourth and fifth electrodes.

Claim 9

Display according to claim 8, characterized in that said first and sixth electrodes (62,52) form a first control capacitance (C2); said second and seventh electrodes (63,53) form a second control capacitance (C3); said third and eighth electrodes (64,54) form a third control capacitance (C4); said fourth and ninth electrodes (65,55) form a fourth control capacitance (C5); said tenth electrode and sixth electrode form a first liquid crystal capacitance (LC2) of said first subpixel (42) said tenth electrode and seventh electrode form a second liquid crystal capacitance (LC3) of said second subpixel (43); said tenth electrode and eighth electrode form a third liquid crystal capacitance (LC4) of said third subpixel (44); said tenth electrode and ninth electrode form a fourth liquid crystal capacitance (LC5) of said fourth subpixel (45); and said tenth electrode and fifth electrode form a fifth liquid crystal capacitance (LC1).