EP0488225A2
Expired / Lapsed
EP
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Clock information transmitting device and clock information receiving device
Assignee: Fujitsu Ltd
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Filing: 1991-11-27
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Granted: —
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Expires: 2011-11-27
Abstract
Abstract A clock information transmitting device coupled to a digital processing circuit which receives a transmission signal and generates a coded transmission signal includes a PLL circuit (17) for generating a first signal and a sampling clock signal, both being synchronized with a synchronizing signal in the transmission signal. The sampling clock signal is used in the digital processing circuit. A clock information generating part (6, 7, 13, 14, 15-1 - 15-10, 16) counts pulses of a transmission clock signal and generates clock information indicating a number of pulses of a transmission clock signal in response to one of the synchronizing signal and the first signal generated by the PLL circuit. A multiplexer (18) outputs a multiplexed signal including the clock information and the coded transmission signal to a transmission path. <IMAGE>
Inventors
- 👤 Yoshiyuki c/o FUJITSU LIMITED Wada
- 👤 Toshihiro c/o FUJITSU KYUSHU DIGITAL Yamanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 21:44
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/40; H04N21/43; H04N21/434; H04N21/4342; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331; H04N21/20; H04N21/23; H04N21/236; H04N21/23602; H04N7/00; H04N7/24; H04N7/52; H04N7/54; H04N7/56
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
174 words
A clock information transmitting device coupled to a digital processing circuit which receives a transmission signal and generates a coded transmission signal, comprising signal separation means (12) for separating a synchronizing signal from the transmission signal, characterized in that said clock information transmitting device comprises: PLL means (17, 17A), coupled to said signal separation means, for generating a first signal and a sampling clock signal, both being synchronized with the synchronizing signal, the sampling clock signal being used in the digital processing circuit; clock information generating means (6, 7, 13, 14, 15-1 - 15-10, 16), coupled to said PLL means, for counting pulses of a transmission clock signal and for generating clock information indicating a number of pulses of a transmission clock signal in response to one of the synchronizing signal and the first signal generated by the PLL means; and multiplexer means (18), coupled to said digital processing circuit and said clock information generating means, for outputting a multiplexed signal including said clock information and said coded transmission signal to a transmission path.
Claim 2
Dependent Claim
138 words
A clock information transmitting device as claimed in claim 1, characterized in that said clock information generating means comprises: clock signal generating means (6, 7) for generating the transmission clock signal and a second signal having a frequency lower than that of the transmission clock signal, the multiplexed signal having a frequency equal to that of the transmission clock signal; counter means (16), coupled to said clock signal generating means, for counting pulses of the transmission clock signal during each period defined by said second signal; and latch means (13, 14, 15-1 - 15-10), coupled to said PLL means and said counter means, for latching a counter value in the counter means in response to said one of the synchronizing signal and the first signal generated by said PLL means, said counter value corresponding to said clock information.
Claim 3
Dependent Claim
62 words
A clock information transmitting device as claimed in claim 2, characterized in that said latch means comprises: first flip-flop means (13, 14) for synchronizing said one of the synchronizing signal and the first signal with the second signal and for generating a synchronized signal; and second flip-flop means (15-1 - 15-10) for latching the counter value in synchronism with said synchronized signal.
Claim 4
Dependent Claim
43 words
A clock information transmitting device as claimed in claim 2, characterized in that said clock generating means comprises: a clock generator (6) generating the transmission clock signal; and a frequency divider (7) for generating the second signal by frequency-dividing the transmission clock signal.
Claim 5
Dependent Claim
59 words
A clock information transmitting device as claimed in claim 1, characterized in that said PLL means comprises: oscillator means (3) for generating the sampling clock signal used in said digital processing circuit and synchronized with the synchronizing signal; and frequency divider means (41), coupled to said oscillator means, for generating the first signal by frequency-dividing the sampling clock signal.
Claim 6
Dependent Claim
90 words
A clock information transmitting device as claimed in claim 5, characterized in that: said frequency divider means comprises a frequency divider (4-2) for generating a third signal by frequency-dividing the first signal, said third signal having a frequency equal to that of the synchronizing signal; and said PLL means comprises phase comparator means (1) for outputting a voltage signal based on a phase difference between the synchronizing signal and the third signal to said oscillator means, a frequency of the sampling clock signal being adjusted based on the voltage signal.
Claim 7
Dependent Claim
57 words
A clock information transmitting means as claimed in claim 5, characterized in that said PLL means comprises phase comparator means (1) for outputting a voltage signal based on a phase difference between the synchronizing signal and the first signal to said oscillator means, a frequency of the sampling clock signal being adjusted based on the voltage signal.
Claim 8
Dependent Claim
35 words
A clock information transmitting means as claimed in any one of claims 1 to 7, characterized in that said transmission signal is a video signal including a horizontal synchronizing signal corresponding to said synchronizing signal.
Claim 9
Dependent Claim
30 words
A clock information transmitting device as claimed in any one of claims 1 - 8, characterized in that the first signal has a frequency twice that of the synchronizing signal.
Claim 10
Dependent Claim
29 words
A clock information transmitting device as claimed in claim 2, characterized in that the second signal has a frequency nearly equal to twice a frequency of the synchronizing signal.
Claim 11
Dependent Claim
53 words
A clock information transmitting means as claimed in any one of claims 1 to 10, characterized by further comprising error correction code generating means (19), coupled to said clock information generating means, for generating an error correction code from said clock information and for adding the error correction code to the clock information.
Claim 12
Dependent Claim
141 words
A clock information receiving device coupled to a processing circuit which decodes a coded transmission signal contained in a multiplexed signal received via a transmission path, characterized in that said clock information receiving device comprises: counter means (31) for counting pulses of a transmission clock signal contained in the multiplexed signal during each predetermined period and for outputting a counter value indicating the number of counted pulses of the transmission clock signal; matching detection means (32), coupled to said counter means, for generating a detection signal when the counter value in the counter means becomes equal to a counter value indicated by clock information included in the multiplexed signal; and PLL means (42), coupled to said matching detection means, for generating a sampling clock signal synchronized with the detection signal, said sampling clock signal being used in the digital processing circuit.
Claim 13
Dependent Claim
92 words
A clock information receiving device as claimed in claim 12, characterized in that said PLL means comprises: oscillator means (26) for generating said sampling clock signal; frequency dividing means (34, 34A), coupled to said oscillator means, for generating a frequency-divided signal from the sampling clock signal; and phase comparator means (22), coupled to said matching detection means and said frequency divider means, for generating a voltage signal based on a phase difference between the detection signal and the sampling clock signal, the voltage signal adjusting a frequency of the sampling clock signal.
References Cited (Backward Citations)
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