EP0487901A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Disk controller using a video ram
Assignee: HP Inc
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Filing: 1991-10-23
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Granted: —
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Expires: 2011-10-23
Abstract
Abstract A disk controller is described with an improved buffer interface between a host processor and a disk drive. The disk controller includes a buffer memory (34) having at least two ports (37, 40), each port capable of bi-directional data transfers to and from the buffer memory. A first data bus (42) is connected to one such port (40) and a second data bus (38) is connected to a second such port (37). A controller (18) operates the buffer memory so that data transfers occur to and from the buffer memory simultaneously over the first and second data busses (42, 38). This thereby enables more efficient data transfers to occur between the host processor and disk drive. <IMAGE>
Inventors
- 👤 Robert J. Lang
- 👤 Robb Mankin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 20:14
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F3/0628; G06F3/0655; G06F3/0656
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
132 words
A disk controller for providing data transfers between a disk memory and a host processor, said disk controller exhibiting improved buffer memory data transfers, the combination comprising: buffer memory means (34) having at least two ports (37, 40), each said port capable of bi-directional data transfers to and from said buffer memory means; first bus means (42) connected to one said port (40) of said buffer memory means (34); second bus means (38) connected to a second said port (37) of said buffer memory means (34), said first and second bus means (42, 38) capable of independent and simultaneous operation; and control means (12, 18) for operating said buffer memory means so that data transfers occur to and from said buffer memory means (34) simultaneously over said first and second bus means.
Claim 2
Dependent Claim
43 words
The disk controller as claimed in Claim 1 wherein said buffer memory means comprises: a video random access memory (VRAM) (34) including DRAM (35) and SAM (36) portions, said VRAM (34) including means for transfer of data between said DRAM and SAM portions.
Claim 3
Dependent Claim
32 words
The disk controller as recited in Claim 2 wherein one said port (40) provides bi-directional access to said SAM and a second said port (37) provides bi-directional access to said DRAM (34).
Claim 4
Dependent Claim
58 words
The disk controller as claimed in Claims 2 or 3 wherein said control means comprises: a microprocessor (12); and a buffer controller (18), said buffer controller (18), under the control of said microprocessor (12), arbitrating data access reguests to said buffer memory and enabling internal data transfers between said SAM (36) and DRAM (35) within said VRAM (34).
Claim 5
Dependent Claim
25 words
The disk controller as recited in Claim 4, wherein said buffer controller (18) provides control and address signals via direct interconnections with said VRAM (34).
Claim 6
Dependent Claim
37 words
The disk controller as claimed in any one of Claims 2 through 5 wherein said first bus means (42) is a data bus for enabling data flow between said VRAM (34) and a host interface module (16).
Claim 7
Dependent Claim
38 words
The disk controller as claimed in any one of Claims 2 through 6 wherein said second bus means (38) is a data bus for enabling data flow between said VRAM (34) and a disk mechanism interface module (22).
Claim 8
Dependent Claim
65 words
The disk controller as recited in any one of the preceding claims, comprising: host interface means (16) connected between said first bus means (42) and a host processor and disk interface means (22) connected between said disk memory and said second bus (38), both said interface means functioning to control access between said buffer memory means (34) and said host processor and disk memory respectively.
References Cited (Backward Citations)
No citation records indexed.
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