EP0487288A2
Expired / Lapsed
EP
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Synchronous dynamic random access memory
Assignee: Oki Electric Industry Co Ltd
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Filing: 1991-11-19
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Granted: —
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Expires: 2011-11-19
Abstract
Abstract A synchronous dynamic random-access memory has transparent latch circuits that latch address signals in synchronization with a clock signal. An X-address is latched following activation of a first control signal ; a Y-address is latched following activation of a second control signal. Data selected by the latched X- and Y-addresses are held in a data latch and output through a tri-state output circuit in synchronization with the clock signal. Data output starts a certain number of clock cycles from activation of the first control signal. The data can be output for one clock cycle, the same data can be output for two or more consecutive clock cycles, or different data can be output in consecutive clock cycles in an order determined by certain bits in the X- and Y-addresses.
Inventors
- 👤 Atsushi C/O Oki Electric Ind. Co. Ltd. Takasugi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 11:45
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408; G11C11/4082; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
137 words
A synchronous dynamic random-access memory that provides data output in response to multiplexed address signals, a first control signal, a second control signal, and a clock signal, comprising: a memory cell array having a plurality of memory cells; address input means for latching said address signals on a first transition of said clock signal selected by said first control signal to generate an X-address, and on a second transition of said clock signal selected by said second control signal to generate a Y-address; decoding means coupled to said memory cell array and said address input means, for selecting one or more memory cells in said memory cell array according to said X-address and said Y-address; and output means coupled to said memory cell array, for outputting data from said memory cells in synchronization with said clock signal.
Claim 2
Dependent Claim
137 words
A synchronous dynamic random-access memory that provides data output in response to multiplexed address signals, a first control signal, a second control signal, and a clock signal, comprising: a memory cell array having a plurality of memory cells; address input means for latching said address signals on a first transition of said clock signal selected by said first control signal to generate an X-address, and on a second transition of said clock signal selected by said second control signal to generate a Y-address; decoding means coupled to said memory cell array and said address input means, for selecting one or more memory cells in said memory cell array according to said X-address and said Y-address; and output means coupled to said memory cell array, for outputting data from said memory cells in synchronization with said clock signal.
Claim 3
Dependent Claim
122 words
The memory of claim 1, wherein said address input means comprises: X-address latch signal generating means for generating an X-address latch signal that becomes active when said clock signal undergoes a certain transition while said first control signal is active, and remains active until said first control signal becomes inactive; Y-address latch signal generating means for generating a Y-address latch signal that becomes active when said clock signal undergoes a certain transition while said second control signal is active, and remains active until said second control signal becomes inactive; first transparent latch means, for latching said address signal in response to said X-address latch signal; and second transparent latch means, for latching said address signal in response to said Y-address latch signal.
Claim 4
Dependent Claim
67 words
The memory of claim 2, wherein said X-address latch signal generating means comprises: a first set-reset flip-flop circuit; an first inverter for inverting said first control signal to generate a first inverted signal that resets said first set-reset flip-flop circuit; and a first logic gate circuit for combining the clock signal and the first inverted signal to generate a signal that sets said first set-reset flip-flop circuit.
Claim 5
Dependent Claim
67 words
The memory of claim 2, wherein said Y-address latch signal generating means comprises: a second set-reset flip-flop circuit; a second inverter for inverting said second control signal to generate a second inverted signal that resets said second set-reset flip-flop circuit; and a second logic gate circuit for combining the clock signal and the second inverted signal to generate a signal that sets said second set-reset flip-flop circuit.
Claim 6
Dependent Claim
40 words
The memory of claim 2, also comprising: third transparent latch means for latching said first control signal in response to said clock signal; and fourth transparent latch means for latching said second control signal in response to said clock signal.
Claim 7
Dependent Claim
56 words
The memory of claim 5, further comprising: delay means coupled to said third transparent latch means, for delaying output of said third latch circuit responsive to said clock signal; and gating means coupled to said second transparent latch means, for gating address input to said second transparent latch means responsive to output of said delay means.
Claim 8
Dependent Claim
88 words
The memory of claim 1, wherein said output means comprises: data latch means for latching data read from said memory cells; output control means for generating an output control signal that becomes active for one cycle of said clock signal, starting a certain number of cycles of said clock signal after a cycle of said clock signal in which said first control signal becomes active; and tri-state output means, enabled and disabled by said output control signal, for external output of data held in said data latch means.
Claim 9
Dependent Claim
27 words
The memory of claim 7, wherein said output control signal becomes active only if said second control signal becomes active after said first control signal becomes active.
Claim 10
Dependent Claim
17 words
The memory of claim 7, wherein said output control signal remains active for just one clock cycle.
Claim 11
Dependent Claim
46 words
The memory of claim 7, wherein said output control signal remains active for just one clock cycle if said second control signal becomes inactive before or during this clock cycle, but otherwise remains active for further clock cycles until said second control signal has become inactive.
Claim 12
Dependent Claim
97 words
The memory of claim 7, wherein said output control means comprises: a series of flip-flop means clocked by said clock signal, for delaying said first control signal; first one-shot pulse generating means, coupled to receive output of a next-to-Iast flip-flop means in said series, for generating a first pulse signal in response thereto; second one-shot pulse generating means, coupled to receive output of a last flip-flop means in said series, for generating a second pulse signal in response thereto; and first set-reset flip-flop means set by said first pulse signal and reset by said second pulse signal.
Claim 13
Dependent Claim
64 words
The memory of claim 11, wherein said output control means also comprises: second set-reset flip-flop means set by said second control signal and reset by said first control signal; further flip-flop means, clocked by said clock signal, for latching output of said second set-reset flip-flop means; and gating means for gating output of said next-to-last flip-flop means by output of said further flip-flop means.
Claim 14
Dependent Claim
96 words
The memory of claim 11, wherein said output control means also comprises: output extending means for generating an output extending signal that becomes active when said first control signal is active, said second control signal is active, and output of said next-to-last flip-flop is active, and becomes inactive if a certain transition of said clock signal occurs when said second control signal is inactive; and OR logic means for modifying said output control signal according to said output extending signal, thereby causing said output control signal to remain active while said output extending signal is active.
Claim 15
Dependent Claim
63 words
The memory of claim 1, wherein said output means comprises: multiple data latch means for simultaneously latching data read from a plurality of said memory cells; consecutive output control means for selecting data latched in said multiple data latch means, different data being selected in different clock cycles; and tri-state output means for externally outputting data selected by said consecutive output control means.
Claim 16
Dependent Claim
34 words
The memory of claim 14, wherein said consecutive output control means selects data in a cyclic order starting from a point determined according to one or more bits of said X-address and said Y-address.
Claim 17
Dependent Claim
37 words
The memory of claim 15, wherein said consecutive output control means selects data in either a forward cyclic order or a reverse cyclic order depending on said one or more bits of said X-address and said Y-address.
Claim 18
Dependent Claim
72 words
The memory of claim 14, wherein said consecutive output control means comprises: decoder means for decoding one or more bits of said X-address and said Y-address to produce decoded outputs; shift register means for storing decoded outputs of said decoder, and rotating said decoded outputs responsive to said clock signal; and output selecting means for selecting data stored in said multiple data latch means according to contents of said shift register means.
Claim 19
Dependent Claim
35 words
The memory of claim 17, wherein said output selecting means comprises a plurality of switches, controlled by contents of said shift register means, for connecting said multiple data latch means to said tri-state output means.
Claim 20
Dependent Claim
43 words
The memory of claim 17, wherein said decoder means also generates a shift control signal, and said consecutive output control means also comprises shift control means for commanding said shift register means to rotate right or left according to said shift control signal.
References Cited (Backward Citations)
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