EP0487022A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A method of simultaneously fabricating an insulated gate-field-effect transistor and a bipolar transistor
Assignee: Texas Instruments Inc
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Filing: 1991-11-19
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Granted: —
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Expires: 2011-11-19
Abstract
Abstract An insulated-gate field-effect transistor (426, 452) has reduced gate oxide stress. According to one embodiment, the control gate (458) has a doped region (460) adjacent the source end of the transistor (452), and an undoped dielectric portion (462) adjacent the gate end. According to another embodiment, the drain end of the conductive gate (434) is disposed on top of a thick insulator region (432) that also acts to mitigate the high electric fields present when the transistor is subjected to a high voltage transient.
Inventors
- 👤 Michael C. Smayling
- 👤 Jack Reynolds
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 04:45
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/671; H10D99/00; H10B; H10B41/00; H10B41/40; H10B41/42; H10D10/00; H10D10/01; H10D10/051; H10D10/40; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/028; H10D30/0281; H10D30/0291; H10D30/60; H10D30/601; H10D30/603; H10D30/64; H10D30/65; H10D30/66; H10D30/663; H10D30/668; H10D64/111; H10D64/115; H10D64/675; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/127; H10D62/13; H10D62/149; H10D62/151; H10D62/152; H10D62/153; H10D62/156; H10D62/157; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; Y; Y10; Y10S; Y10S148/00; Y10S148/009; Y10S148/082
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
136 words
An insulated-gate field-effect transistor with reduced gate insulator stress formed at a face of a semiconductor layer of a first conductivity type, comprising: a thin gate insulator formed on said face; a control gate formed on said thin gate insulator and having first and second lateral margins; a source region formed in said semiconductor layer to be of a second conductivity type opposite said first conductivity type and to be adjacent said second lateral margin of said control gate; a drain region formed in said semiconductor layer to be of said second conductivity and to be substantially adjacent said first lateral margin of said control gate; and a channel region of said first conductivity type formed between said source region and said drain region, said control gate operable to control the conductance of said channel region.
Claim 2
Dependent Claim
53 words
The transistor of Claim 1 and wherein a first portion of said control gate adjacent said first lateral margin is formed of a substantially dielectric material, and a second portion of said control gate adjacent said second lateral margin is formed of a substantially conductive material, said first portion adjoining said second portion.
Claim 3
Dependent Claim
43 words
The transistor of Claim 1 or Claim 2 and including a thick insulator region formed on said face, said thick insulator having first and second opposed lateral margins adjacent said face and a top face spaced from said face of said semiconductor layer.
Claim 4
Dependent Claim
33 words
The transistor of Claim 3 and wherein said thin gate insulator is formed on a portion of said face of said semiconductor layer adjacent said first lateral margin of said thick insulator region.
Claim 5
Dependent Claim
52 words
The transistor of Claim 3 of Claim 4 and wherein said control gate is formed across said first lateral margin, a portion of said control gate being disposed on said top face of said thick insulator region and a portion of said control gate being disposed on said thin gate insulator layer.
Claim 6
Dependent Claim
34 words
The transistor of any preceding claim and further comprising: a tank of said second conductivity type formed in said semiconductor layer to laterally enclose said drain region, said tank extending underneath said control gate.
Claim 7
Dependent Claim
24 words
The transistor of Claim 6, wherein a portion of said tank is disposed beneath a portion of said first portion of said control gate.
Claim 8
Dependent Claim
20 words
The transistor of any preceding claim and wherein said first portion of said control gate comprises substantially undoped polycrystalline silicon.
Claim 9
Dependent Claim
23 words
The transistor of any preceding claim and wherein said second portion of said control gate comprises polycrystalline silicon rendered substantially conductive by doping.
Claim 10
Dependent Claim
109 words
A process for fabricating an insulated-gate field-effect transistor having reduced gate insulator stress, comprising the steps of: forming a control gate to be insulatively adjacent a semiconductor channel region of the transistor so as to be operable to control the conductance thereof after the process is completed; selectively modifying a first portion of the control gate to be substantially conductive; during said step of selectively modifying, masking a second portion of the control gate such that it will remain substantially nonconductive; forming a semiconductor source region adjacent the first portion of the control gate; and forming a semiconductor drain region substantially adjacent the second portion of the control gate.
Claim 11
Dependent Claim
19 words
The process of Claim 10, wherein said step of selectively modifying, comprises doping the first portion with a dopant.
Claim 12
Dependent Claim
85 words
The process of Claim 10 or 11, and further comprising the steps of: forming a first tank region in which the semiconductor portions of the insulated gate field-effect transistor are to be contained; forming a second tank region of a second conductivity type opposite the conductivity type of the first tank region, and to be contained within the first tank region; and forming the control gate such that a lateral margin of the second tank region is beneath the first portion of the control gate.
Claim 13
Dependent Claim
183 words
A process for fabricating an insulated-gate field-effect transistor, having reduced gate insulator stress, at a face of a semiconductor layer having a first conductivity type, comprising the steps of: forming a relatively thick insulator region on said face, said thick insulator region having first and second opposed lateral margins and a top face spaced from said face of said semiconductor layer; forming a relatively thin gate insulator layer on a portion of said face of said semiconductor layer adjacent said first lateral margin; forming a conductive control gate across said first lateral margin, a portion of said control gate disposed on said top face of said thick insulator region, a portion of said control gate disposed on said thin gate insulator layer; forming a source region to be of a second conductivity type opposite said first conductivity type and to be adjacent said portion of said control gate disposed on said thin gate insulator; and forming a drain region on said face to be of said second conductivity type and to be disposed adjacent said second lateral margin of said thick insulator region.
Claim 14
Dependent Claim
122 words
The process of Claim 13, and further comprising the steps of: forming a tank region to be of said second conductivity type in said semiconductor layer and to create a tank area on said face of said semiconductor layer; forming said thick insulator region such that the first and second lateral margins thereof are interiorly spaced from corresponding first and second lateral margins of the tank area; forming said thin gate insulator layer to at least partially laterally extend outward from said tank area; forming said source region to be spaced from said first lateral margin of said tank area by a channel region of the first conductivity type; and forming the drain region to be laterally enclosed by the tank area.
References Cited (Backward Citations)
No citation records indexed.
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