Patent US774865A successfully refreshed from Google Patents.
EP0486145A2
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Direct memory access controller
Assignee: International Business Machines Corp
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Filing: 1991-10-01
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Granted: —
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Expires: 2011-10-01
Abstract
Abstract An improved multi-channel direct memory access (DMA) controller for data processing systems provides adaptive pipelining and time overlapping of operations performed relative to communication channels. Registers and resources used to pipeline communication data and control signals relative to plural channels are adaptively shared relative to a single channel when command chaining is required relative to that channel. In command chaining a plural word command, termed a Device Control Block (DCB), is fetched from an external system memory via a bus having severe time constraints relative to potential real time requirements of the channels. Pipelining and time overlapping of channel operations, relative to plural channels, increases the effective rate of transfer at the bus interface to the system memory, and thereby allows for the controller to be used for applications in which throughput requirements and bus access constraints could otherwise conflict.
Inventors
- 👤 Joseph Kevin Farrell
- 👤 Jeffrey Scott Gordon
- 👤 Daniel Clair Kuhl
- 👤 Timothy Vincent Lee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 17:02
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
472 words
A multi-channel DMA (Direct Memory Access) controller for controlling access to a data processing system memory via a system bus connectable to plural devices including said controller, said DMA controller comprising: random access buffer memory means for storing data and control information relative to a plurality of channels served by said controller; said channels including plural input channels carrying data to be stored in said system memory and plural output channels carrying data fetched from said system memory; bus control means coupled to said bus for arbitrating for and controlling said bus and for operating through said bus to transfer data to said system memory relative to individual said input channels and to fetch data from said system memory relative to individual said output channels; DMA control (DMAC) means having internal registers for storing data and control information relative to any one of said channels; said DMAC means being coupled to said buffer memory means for writing data from said internal registers into said buffer memory means relative to any of said output channels, for fetching data from said buffer memory means to said internal registers relative to any of said input channels, and for transferring control information bidirectionally between said buffer memory means and said internal registers relative to any of said channels; said DMAC means including means responsive to control information in said registers associated with a said channel for directing operations of said bus control means relative to an address in system memory allocated to said associated channel; and DMA data buffer (DMADB) means having internal registers for holding data and control information associated with any of said channels; said DMADB means interfacing between said bus control means and said DMAC means for transferring data and control information relative to individual said channels between said DMAC means and said bus control means; said DMADB and bus control means operating in tight coupled synchronism, and both operating in relative asynchronism to said DMAC means; said DMADB means operating in response to control signals received from said DMAC means relative to any said channel to receive data and control information of that channel in its internal registers from internal registers of said DMAC means, to allow data and control information of that channel to be transferred from its internal registers to internal registers of said DMAC means, and to cooperate with said bus control means while effectively decoupled from said DMAC means to carry out an operation relative to said system memory via said bus; whereby while said operation is being performed by said DMADB and bus control means relative to said system memory, said internal registers of said DMAC means are free to receive data and control information relative to another said channel for preparing a subsequent operation by said DMADB and bus control means relative to said another channel.
Claim 2
Dependent Claim
115 words
A multi-channel DMA controller in accordance with claim 1 wherein: said DMAC means comprises swap control means for transferring control information and data relative to one channel from said internal registers of said DMAC means to said internal registers of said DMADB means, while at the same time transferring control information and data relative to another channel from said internal registers of said DMADB means to said internal registers of said DMAC means, whereby said DMAC, DMADB and bus control means can operate in time overlap relative to said one and another channels to carry out data transfer operations between said buffer memory means and said system memory simultaneously relative to both of said channels.
Claim 3
Dependent Claim
127 words
A multi-channel DMA controller in accordance with claim 1 or 2, wherein said buffer memory means is accessible to devices isolated from said bus and said DMA controller, said controller including: DMA request queueing (DMARQ) means coupled to said external devices for storing data transfer requests from said external devices relative to said input and output channels, in association with transfers of data between said devices and said buffer memory means; said DMAC means including means responsive to requests stored in said DMARQ means for initiating actions by said DMAC means relative to said buffer memory means and said channels, whereby data is transferred to and from said buffer memory means at a pace coordinated with requirements of said external devices and timing constraints on said bus.
Claim 4
Dependent Claim
319 words
A multi-channel DMA controller in accordance with claim 1, 2 or 3 wherein said control information stored relative to at least one of said channels includes a command which may have a chained association with another command stored in said system memory relative to the same channel; each of said associated commands defining data unit transfer operations of said DMAC, DMADB and bus control means relative to a block of data unit storage spaces in said system memory allocated to the associated channel, and each of said commands including data unit count information defining a number of data units to be transferred relative to said block; said DMAC means including: means for fetching the associated command stored in said buffer memory means to internal registers of said DMAC means; means responsive to the command in said registers for initiating an operation by said DMADB and bus control means relative to a system memory data unit address designated by said command, said address being an address in the block of addresses allocated to the associated channel; means operative while said operation is being initiated for modifying said address and unit count in said registered command; means for storing said registered command, with said modified address and unit count back in said buffer memory means; means responsive to information from said modified count that said block of system memory spaces is exhausted and to information from said registered command indicating chained association to another command and to information in said registered command designating the location in system memory of said associated another command to initiate an operation by said DMADB and bus control means for fetching said another command from said system memory successively through said internal registers of said DMADB and DMAC means for enabling said DMAC means to direct further data transfer operations relative to another block of data unit spaces in system memory allocated to the associated channel.
Claim 5
Dependent Claim
70 words
A multi-channel DMA controller in accordance with claim 4 wherein each of said chained commands comprises a Data Control Block (DCB) consisting of plurality of data units of control information, retrieval of which requires internal registers in both said DMAC and DMADB means to be used simultaneously; whereby said registers are unavailable for service to a channel other than the channel associated with the DCB of the command being retrieved.
Claim 6
Dependent Claim
67 words
A multi-channel DMA controller in accordance with claim 5 wherein upon retrieval of a last unit of a DCB representing a chained command, said internal registers of said DMAC means are set with information defined by all of the units of the retrieved DCB, enabling said DMAC to immediately direct the DMADB and bus control means to initiate a data unit transfer operation defined by said DCB.
Claim 7
Dependent Claim
120 words
A multi-channel DMA controller in accordance with any one of the preceding claims wherein said bus control means comprises: means for detecting an idle condition occurring when the bus control means has control of the bus, has finished an operation requested by said DMAC means relative to one of said channels and has not received a request for another operation from said DMAC means via said DMADB means for a predetermined interval of time representing a fraction of the time required by said DMAC means to prepare a request for another operation relative to another one of said channels; and means responsive to detection of said idle condition for conditioning said bus control means to release control of said bus.
Claim 8
Dependent Claim
263 words
A DMA controller in accordance with claim 7 wherein said DMAC leans includes means for initiating a chained command fetching operation relative to a said channel requiring multiple control data unit transfers on said bus in uninterrupted succession, and means for initiating single data transfer operations relative to each of said channels requiring single data unit transfers on said bus, and wherein said bus control means includes: timer means responsive to a preempt signal on said bus while said bus control means has control of said bus for initiating a timeout of predetermined duration; said preempt signal indicating external bids by other devices for control of said bus; means responsive to the output of said timer representing an elapsed time less than a first predetermined time for conditioning said bus control means to respond to requests for either single data unit transfers or plural unit chained command transfers presented by said DMAC means via said DMADB means; means responsive to the output of said timer representing an intermediate elapsed time greater than said first predetermined time but less than a second predetermined time for conditioning said bus control means to respond only to requests for single data unit transfers but not to requests for chained command transfers; and wherein said means for conditioning said bus control means to release control of said bus is effective to condition said release either in response to detecting said idle condition or in response to detecting that said bus control means has finished an operation and said timer elapsed time is greater than said second predetermined time.
Claim 9
Dependent Claim
253 words
A multi-channel DMA controller in accordance with any one of the preceding claims wherein: said buffer memory means comprises first and second separately accessible Random Access Memories (RAM's); said first RAM having a pair of unit storage spaces dedicated to each of said channels for storing a unit of data and a unit of control information relative to the associated channel; said unit of control information comprising a portion of a command for controlling operations relative to the respective channel, said command consisting of 3 units of control information; said second RAM having a pair of unit storage spaces dedicated to each of said channels for storing two units of control information constituting a remaining portion of the command associated with the respective channels; and wherein said DMAC means comprises means for simultaneously applying requests to said first and second RAM for initiating retrieval of all 3 units of control information constituting a command associated with one of said channels and placement of said units in the internal registers of said DMAC means in about the same time on the average as the time needed by said DMADB and bus control means to carry out an operation relative to another one of said channels via said bus, while said bus control means has control of said bus; whereby said DMAC means can act to prepare for an operation relative to one channel at about the same time that said DMADB and bus control means are carrying out an operation relative to another channel.
Claim 10
Dependent Claim
162 words
A multi-channel DMA controller in accordance with claim 9 wherein: said DMAC means comprises means effective when the internal registers of said DMAC means are prepared with command information associated with one channel for detecting when said DMADB and bus control means have completed an operation relative to another channel; and means responsive to detection of said completion by said detecting means for controlling a swap transfer operation between internal registers of said DMAC means and said DMADB means, causing said internal registers of said DMADB means to receive data and control information relative to said one channel and said internal registers of said DMAC means to receive data and control information relative to said another channels; whereby operations between said another channel and said first and second RAM's can be completed by said DMAC means while at the same time operations between said one channel and said system memory means can be carried out by said DMADB and bus control means.
Claim 11
Dependent Claim
142 words
A multi-channel bus controller in accordance with claim 10 wherein: said 3 units of command information stored in said first and second RAMs relative to said one channel are associated in a chained relation to another 3-unit block of information stored in said system memory relative to said one channel; and said DMAC means comprises: means for detecting when data transfers relative to said one channel defined by the 3 units stored in said first and second RAM's are exhausted; and means responsive to detection that said transfers are exhausted for initiating an uninterrupted retrieval of the 3 units of the chained command information stored in said system memory, via the internal registers of both said DMADB and DMAC means; whereby said registers are effectively dedicated exclusively to the retrieval of said chained 3 units while said chained units are being retrieved.
Claim 12
Dependent Claim
357 words
A multi-channel DMA (direct memory access) controller for controlling access to memory of a data processing system relative to data transfer channels having real time constraints, and for conducting data transfers relative to said system memory via a bus having access time constraints capable of conflicting with said real time constraints if said channels are served without time overlap by said controller, said controller comprising: a RAM buffer store having space allocated to each said channel for storing control information and data relative to each channel; first means coupled to said buffer store for accessing said store relative to individual said channels and transferring control information and data to and from said store relative to respective channels, said means containing registers which are time shared relative to said channels for holding control information associated with any one of said channels at any time and data in transit relative to that channel; second means coupled between said first means and said bus for receiving portions of said control information from said first means and for operating in response to said control information to control said bus and transfer data between said first means and said system memory via said bus, said second means containing registers which are time shared relative to said channels for holding control information associated with one of said channels and data in transit relative to that channel; said registers in said first and second means forming a pipeline in which data can be transferred simultaneously relative to a plurality of said channels; and third means operating relative to said first and second means to cause said first and second means to swap control information and data at discrete instants of time relative to two of said channels; whereby said first and second means can operate relative to respective parts of said pipeline in time overlap to conduct data transfer operations between said buffer store and said system memory relative to said two channels simultaneously, and thereby complete said operations relative to said two channels in less time than would otherwise be required if the data transfers relative to the two channels were conducted sequentially.
References Cited (Backward Citations)
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