A method of fabricating a field-effect transistor

Claim 1

A method of fabricating a field-effect transistor from a structure in which there is a monocrystalline semiconductor region of a first conductivity type, a portion of the semiconductor region being an intended channel for the transistor, the method comprising the steps of: providing a first shield over the semiconductor region at least partially along its upper surface generally above the intended channel; introducing (a) a first impurity of the first conductivity type and (b) a first impurity of a second conductivity type opposite to the first conductivity type into the semiconductor region through its upper surface using the first shield to substantially prevent the first impurities from passing through the directly underlying section of the upper surface of the semiconductor region in order to form (a) a pair of laterally separated initial protection zones of the first conductivity type and (b) a pair of laterally separated surface-adjoining initial source/drain extension zones of the second conductivity type respectively corresponding to the initial protection zones; providing a second shield over the semiconductor region along its then-existing upper surface generally above the intended channel such that, along the length of the channel, the second shield has a greater width than the first shield; and introducing a second impurity of the second conductivity type into the semiconductor region through its then-existing upper surface using the second shield to substantially prevent the second impurity from passing through the directly underlying section of the then-existing upper surface of the semiconductor region in order to form a pair of laterally separated surface-adjoining main source/drain zones of the second conductivity type respectively corresponding to the initial extension zones, each main zone partially overlapping the corresponding extension zone after the four steps are completed to form a combined surface-adjoining source/drain zone of the second conductivity type, at least part of each initial protection zone remaining after the four steps are completed so as to define a final protection zone of the first conductivity type, each final protection zone being fully surrounded along its lateral and lower surfaces either by the corresponding combined zone or by the corresponding combined zone and dielectric material of the structure.

Claim 2

A method of fabricating a field-effect transistor from a structure in which there is a monocrystalline semiconductor region of a first conductivity type, a portion of the semiconductor region being an intended channel for the transistor, the method comprising the steps of: providing a first shield over the semiconductor region at least partially along its upper surface generally above the intended channel; introducing (a) a first impurity of the first conductivity type and (b) a first impurity of a second conductivity type opposite to the first conductivity type into the semiconductor region through its upper surface using the first shield to substantially prevent the first impurities from passing through the directly underlying section of the upper surface of the semiconductor region in order to form (a) a pair of laterally separated initial protection zones of the first conductivity type and (b) a pair of laterally separated surface-adjoining initial source/drain extension zones of the second conductivity type respectively corresponding to the initial protection zones; providing a second shield over the semiconductor region along its then-existing upper surface generally above the intended channel such that, along the length of the channel, the second shield has a greater width than the first shield; and introducing a second impurity of the second conductivity type into the semiconductor region through its then-existing upper surface using the second shield to substantially prevent the second impurity from passing through the directly underlying section of the then-existing upper surface of the semiconductor region in order to form a pair of laterally separated surface-adjoining main source/drain zones of the second conductivity type respectively corresponding to the initial extension zones, each main zone partially overlapping the corresponding extension zone after the four steps are completed to form a combined surface-adjoining source/drain zone of the second conductivity type, at least part of each initial protection zone remaining after the four steps are completed so as to define a final protection zone of the first conductivity type, each final protection zone being fully surrounded along its lateral and lower surfaces either by the corresponding combined zone or by the corresponding combined zone and dielectric material of the structure.

Claim 8

A method of fabricating a field-effect transistor from a structure that comprises (a) a monocrystalline semiconductor region of a first conductivity type, (b) a gate dielectric layer situated along an upper surface of the semiconductor region, and (c) a patterned gate electrode situated on the gate dielectric layer, the method comprising steps of: initially introducing (a) a first impurity of a first conductivity type and (b) a first impurity of a second conductivity type opposite to the first conductivity type into the semiconductor region through its upper surface using the gate electrode and any dielectric material along the sidewalls of the gate electrode as a shield to substantially prevent the first impurities from passing through the directly underlying section of the upper surface of the semiconductor region in order to form (a) a pair of laterally separated initial protection zones of the first conductivity type and (b) a pair of laterally separated initial source/drain extension zones respectively corresponding to the initial protection zones and extending to the upper surface of the semiconductor region; subsequently providing dielectric spacers along the sidewalls of the gate electrode to an average width greater than the average thickness of any dielectric material along the sidewalls of the gate electrode during the initial introducing step; and further introducing a second impurity of the second conductivity type into the semiconductor region through its then-existing upper surface using the gate electrode and the spacers as a shield to substantially prevent the second impurity from passing through the directly underlying section of the then-existing upper surface of the semiconductor region in order to form a pair of laterally separated main source/drain zones of the second conductivity type respectively corresponding to the initial extension zones and extending to the then-existing upper surface of the semiconductor region, each main zone partially overlapping the corresponding extension zone to form a combined source/drain zone of the second conductivity type, at least part of each protection zone remaining after the further introducing step so as to define a final protection zone of the first conductivity type, each final protection zone being fully surrounded along its lateral and lower surfaces either by the corresponding combined zone or by the corresponding combined zone and dielectric material of the structure.

Claim 9

A method of fabricating a field-effect transistor from a structure that comprises (a) a monocrystalline semiconductor region of a first conductivity type, (b) a gate dielectric layer situated along an upper surface of the semiconductor region, and (c) a patterned gate electrode situated on the gate dielectric layer, the method comprising steps of: initially introducing (a) a first impurity of a first conductivity type and (b) a first impurity of a second conductivity type opposite to the first conductivity type into the semiconductor region through its upper surface using the gate electrode and any dielectric material along the sidewalls of the gate electrode as a shield to substantially prevent the first impurities from passing through the directly underlying section of the upper surface of the semiconductor region in order to form (a) a pair of laterally separated initial protection zones of the first conductivity type and (b) a pair of laterally separated initial source/drain extension zones respectively corresponding to the initial protection zones and extending to the upper surface of the semiconductor region; subsequently providing dielectric spacers along the sidewalls of the gate electrode to an average width greater than the average thickness of any dielectric material along the sidewalls of the gate electrode during the initial introducing step; and further introducing a second impurity of the second conductivity type into the semiconductor region through its then-existing upper surface using the gate electrode and the spacers as a shield to substantially prevent the second impurity from passing through the directly underlying section of the then-existing upper surface of the semiconductor region in order to form a pair of laterally separated main source/drain zones of the second conductivity type respectively corresponding to the initial extension zones and extending to the then-existing upper surface of the semiconductor region, each main zone partially overlapping the corresponding extension zone to form a combined source/drain zone of the second conductivity type, at least part of each protection zone remaining after the further introducing step so as to define a final protection zone of the first conductivity type, each final protection zone being fully surrounded along its lateral and lower surfaces either by the corresponding combined zone or by the corresponding combined zone and dielectric material of the structure.