Semiconductor memory device

Claim 2

A semiconductor memory device according to claim 1, characterized in that said first source interconnection (14) extends in the direction crossing said word line (12).

Claim 3

A semiconductor memory device according to claim 1, characterized in that said second source interconnection (17) is provided for each word line (12) or for every specified number of adjacent word lines (12), and is independently supplied with a different potential according to the input address.

Claim 4

A semiconductor memory device according to claim 1, characterized in that said memory cell (11) is a nonvolatile memory cell capable of erasing and rewriting data.

Claim 5

A semiconductor memory device comprising: a memory cell array composed of a plurality of memory cells, each of which has a common source diffused region (26) extending in a specified direction, enables the erasing and rewriting of data, and in an erase operation, has at least one source diffused layer (26) applied with a higher voltage than the source potentials of unselected memory cells; a plurality of word lines (12), each of which extends in parallel with said common source diffused region (26) and is connected to and shared by the gates of said plurality of memory cells (11); first decoding means for selecting said word line (12) according to the input address; a plurality of first source interconnections (14) composed of a first metal interconnection layer electrically connected to said common source diffused region (26); a plurality of second source interconnections (17) that is composed of a second metal interconnection layer electrically connected to said first source interconnection (14), and extends in parallel with said word line (12); and second decoding means for selectively applying a high voltage to only one second source interconnection (17) corresponding to the input address and a low voltage to the remaining second source interconnections (17) in an erase operation.

Claim 6

A semiconductor memory device according to claim 5, characterized in that said plurality of first source interconnections (14) extend in the direction crossing said word line (12).

Claim 7

A semiconductor memory device according to claim 5, characterized in that said second decoding means is supplied with a first control signal for controlling the erase mode, as well as said input address.

Claim 8

A semiconductor memory device according to claim 5, characterized in that said second decoding means is positioned next to said memory cell array.

Claim 9

A semiconductor memory device according to claim 5, characterized in that said word line (12) is composed of a main word line (MWL) and a plurality of section word lines (SWL), and said second decoding means is supplied with the signal on said main word line (MWL) as said input address.

Claim 10

A semiconductor memory device according to claim 5, characterized in that said memory cell array is divided into a plurality of sections in the direction of said word line (12), with each section being provided with said second source interconnection (17).

Claim 11

A semiconductor memory device according to claim 5, characterized in that in an erase operation, a high voltage is applied either to only some of said second source interconnections (17) selectively or to all second source interconnections (17) in parallel.

Claim 12

A semiconductor memory device according to claim 5, characterized in that in an erase operation, said second decoding means applies a high voltage either to one of said second source interconnections (17) selectively, corresponding to the input address, or to all second source interconnections (17) in parallel.