EP0477873A2
Expired / Lapsed
EP
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Vertical type semiconductor device
Assignee: Denso Corp
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Filing: 1991-09-24
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Granted: —
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Expires: 2011-09-24
Abstract
Abstract A vertical type semiconductor device capable of greatly decreasing the on-resistance without impairing the breakdown voltage of the element. In the fundamental DMOS cells 2 that control the current to constitute the vertical semiconductor device, through hole cells 3 are arranged along the sides of the cell that form a channel 21. The through hole cell 3 has a through hole 23 extending from the surface of an n⁻-type drift region toward an n⁺-type drain region 12, and has an n⁺-type through hole region 25 that is formed by diffusing impurities from the inner wall of the through hole 23 and that is continuous to the n⁺-type drain region 12. A breakdown voltage of the element is maintained by the n⁻-type drift region 11 between a p-type well region 13 and the n⁺-type through hole region 25 or the n⁺-type drain region 12. Owing to the disposition of the through hole cells 3, the JFET resistance component becomes negligibly small between the DMOS cells 2 neighboring along the sides of the cells despite the fact that the cells are finely formed, and a small on-resistance is exhibited.
Inventors
- 👤 Norihito Tokura
- 👤 Kunihiko Hara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 23:06
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/668; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10D62/124; H10D62/126; H10D62/127; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/256
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
242 words
A vertical type semiconductor device wherein a semiconductor substrate of a first type of conduction consists of a layer of a high impurity concentration and a layer of a low impurity concentration, the layer of said high impurity concentration serves as a drain region, the surface of the layer of said low impurity concentration forms a main surface, a well region of a second type of conduction is formed in a portion of said main surface, a source region of the first type of conduction is formed in a portion of the surface of said well region, a gate electrode is formed on a periphery of said well region of the second type of conduction via an insulating film in order to form a channel region on the periphery of said well region, the layer of said low impurity concentration forms a drift region between said well region of the second type of conduction and said drain region, and a current between the drain and the source is controlled by applying a voltage to said gate electrode, and wherein a hole is formed extending from said main surface between said neighboring well regions up to said drain region passing through the layer of said low impurity concentration (drift region), and the electric resistance in the lengthwise direction of said hole is set to be smaller than the electric resistance of the layer of said low impurity concentration inside or around said hole.
Claim 2
Dependent Claim
38 words
A vertical type semiconductor device according to claim 1, wherein the position of said main surface between said neighboring well regions is set to be higher than the position of said channel region to constitute a recessed structure.
Claim 3
Dependent Claim
111 words
A vertical type semiconductor device according to claim 1, wherein said well regions of the second type of conduction are regularly arranged on a portion of said main surface, a through hole region having said hole at the center is arranged in a portion sandwiched by said two neighboring well regions of the second type of conduction under said arranged condition, and said well regions of the second type of conduction and said through hole regions are alternatingly arranged in the vertical and lateral directions in a manner such that the portions will decrease when said two neighboring well regions of the second type of conductions are adjacent to each other.
Claim 4
Dependent Claim
111 words
A vertical type semiconductor device according to claim 2, wherein said well regions of the second type of conduction are regularly arranged on a portion of said main surface, a through hole region having said hole at the center is arranged in a portion sandwiched by said two neighboring well regions of the second type of conduction under said arranged condition, and said well regions of the second type of conduction and said through hole regions are alternatingly arranged in the vertical and lateral directions in a manner such that the portions will decrease when said two neighboring well regions of the second type of conductions are adjacent to each other.
Claim 5
Dependent Claim
29 words
A vertical type semiconductor device according to any one of claim 1, wherein the through hole diffusion region of the first type of conduction is formed around said hole.
Claim 6
Dependent Claim
29 words
A vertical type semiconductor device according to any one of claim 3, wherein the through hold diffusion region of the first type of conduction is formed around said hole.
Claim 7
Dependent Claim
29 words
A vertical type semiconductor device according to any one of claim 4, wherein the through hole diffusion region of the first type of conduction is formed around said hole.
Claim 8
Dependent Claim
49 words
A vertical type semiconductor device according to any one of claim 1 wherein the interior of said hole is charged with a conductor having a small resistance such as a metal that comes into ohmic contact with the surface of a semiconductor on the side surface of said hole.
Claim 9
Dependent Claim
245 words
A vertical type semiconductor device comprising: a drain region of a first type of conduction; a semiconductor layer of the first type of conduction formed on one main surface of said drain region and has an impurity concentration lower than that of said drain region to serve as a drift region; a current control cell region that controls the current between the drain and the source and is comprised of a well region of a second type of conduction that is connected to one region of said semiconductor layer buried in the surface of said semiconductor layer, and has a PN junction relative to said semiconductor layer, the PN junction terminating in the surface of said semiconductor layer; a source region of the first type of conduction having a PN junction relative to said well region, the PN junction terminating in the surface of said well region; and an insulated gate structure constituted on a channel region that consists of the surface of said well region between the drift region and the source region, and a low-resistance cell region having a low-resistance region of the first type of conduction that is set in another region of said semiconductor layer to correspond to said channel region of said current control cell region extending from the surface of said semiconductor layer up to said drain region, and has an impurity concentration higher than that of said semiconductor layer that forms said drift region via said drift region.
Claim 10
Dependent Claim
45 words
A vertical type semiconductor device according to claim 9, wherein the breakdown voltage of said vertical type semiconductor device is set depending upon the impurity concentration of said semiconductor layer and the distance of said semiconductor layer between said well region and said low-resistance region.
Claim 11
Dependent Claim
31 words
A vertical type semiconductor device according to claim 9, wherein said current control cell region has a polygonal cellular shape such that said channel regions are formed along the sides thereof.
Claim 12
Dependent Claim
28 words
A vertical type semiconductor device according to claim 11, wherein said low-resistance cell regions are arranged to be opposed to all sides of said current control cell regions.
Claim 13
Dependent Claim
40 words
A vertical type semiconductor device according to claim 12, wherein said current control cell regions and said low-resistance cell regions both have a square cellular shape and are alternatingly arranged in the vertical and lateral directions on said semiconductor layer.
Claim 14
Dependent Claim
31 words
A vertical type semiconductor device according to claim 12, wherein said current control cell regions have an orthohexagonal cellular shape and said low-resistance cell regions have an equilateral triangular cellular shape.
Claim 15
Dependent Claim
46 words
A vertical type semiconductor device according to claim 12, wherein the current control cell regions neighboring one another at the corners of the polygonal cellular shape thereof maintain such a distance among themselves that the depletion layers overlap each other when said device is turned off.
Claim 16
Dependent Claim
28 words
A vertical type semiconductor device according to claim 9, wherein the surfaces of said low-resistance cell regions are higher than the surfaces of said current control cell regions.
Claim 17
Dependent Claim
40 words
A vertical type semiconductor device according to claim 9, wherein said low-resistance region is formed by the diffusion from the inner wall of the hole that is formed from the surface of said semiconductor layer extending toward said drain region.
Claim 18
Dependent Claim
198 words
A vertical type semiconductor device comprising: a first semiconductor layer constituted by a semiconductor layer of a first type of conduction that forms a drain region; a second semiconductor layer of the first type of conduction that is formed on the main surface of said first semiconductor layer and has an impurity concentration lower than the impurity concentration of said drain region; well regions constituted by a plurality of isolated semiconductors of a second type of conduction that are formed from the main surface of said second semiconductor layer inward of said second semiconductor layer; source regions constituted by a plurality of semiconductors of the first type of conduction that are formed in said well regions; and a gate electrode provided adjacent to a junction portion between said well region and said source region in order to form a channel region at said junction portion; wherein said vertical type semiconductor device further has at least one hole portion formed in a region other than the regions where said plurality of well regions are formed in said second semiconductor layer, said hole portion extending from the main surface of said second semiconductor layer up to said first semiconductor layer.
Claim 19
Dependent Claim
32 words
A vertical type semiconductor device according to claim 18, wherein said hole portion has a resistance that is smaller than the resistance of said second semiconductor layer that forms said drift region.
Claim 20
Dependent Claim
19 words
A vertical type semiconductor device according to claim 18, wherein said hole portion is charged with a low-resistance material.
References Cited (Backward Citations)
No citation records indexed.
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