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EP0476625A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

A semiconductor device comprising interconnections

Assignee: NEC Corp
•
Filing: 1991-09-18
•
Granted: —
•
Expires: 2011-09-18
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Abstract

Abstract In a semiconductor device, an inter-level insulating film (3) is formed at solid crossing points between upper level interconnections (6) and lower-level interconnections (2), excepting via hole portions. This means that mechanical support between interconnection levels is given by solid crossing points between interconnections. For this, a semiconductor device having high durabilities against thermal and mechanical impacts can be obtained. Further, since inter-level regions other than the solid crossing points are made vacant to form a cavity, coupling capacity can be reduced to 1/3 to 1/2 of an ordinary multilevel interconnections wherein inter-level regions are fully filled with an inter-level insulating film.

Inventors

  • 👤 Takuya c/o NEC Corporation Katoh

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 07:29
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42; H10W20/495

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 118 words
A semiconductor device comprising (a) a lower-level inter-level insulating film formed on a semiconductor substrate, (b) lower-level interconnections formed on the lower-level inter-level insulating film (a), (c) an upper-level inter-level insulating film formed on the lower-level interconnections (b), and (d) an upper-level interconnections formed on the upper-level inter-level insulating film (c) to form solid crossing points with the lower-level interconnections (b) and connected to the lower-level interconnections (b) through via holes formed in the upper-level inter-level insulating film (c); said upper-level inter-level insulating film (c) being formed only at solid crossing points between the upper-level interconnections (d) and the lower-level interconnections (b) to form a cavity between the lower-level inter-level insulating film (a) and the upper-level interconnections (d).
Claim 2
Dependent Claim 224 words
A process for the production of a semiconductor device comprising steps of: (1) forming on a semiconductor substrate, a lower-level inter-level insulating film of an inorganic material, (2) forming on the lower-level inter-level insulating film, a lower-level interconnection layer, an upper-level inter-level insulating film and a photoresist film in this order, (3) patterning the photoresist film to form a first mask, (4) patterning by means of this first mask, the upper-level inter-level insulating film and the lower-level interconnection layer to form lower-level interconnections, (5) forming an organic insulating film on an entire surface including the patterned upper-level inter-level insulating film, after removing the first mask, (6) etching the organic insulating film to expose the surface of the patterned upper-level inter-level insulating film, (7) forming via holes in the exposed upper-level inter-level insulating film, (8) forming an upper level interconnection layer on the entire surface and at the same time filling the via holes with this upper-level interconnection layer, (9) forming on this upper-level interconnection layer, a photoresist film and patterning the same to form a second mask, (10) patterning by means of this second mask, the upper-level interconnection layer and the upper-level inter-level insulating film to form upper-level interconnections elongated in the direction to form solid crossing points with the lower-level interconnections, and (11) removing the second mask and the remaining organic insulating film.

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