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EP0475688A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method for manufacturing memories with thin film transistors

Assignee: Sharp Corp
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Filing: 1991-09-05
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Granted: —
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Expires: 2011-09-05
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Abstract

Abstract A method for manufacturing a TFT type memory providing steps of (i) depositing a first insulating layer over a semiconductor substrate having a polysilicon gate formed by a first polysilicon film, and then opening a first contact hole so as to form a first insulating film, (ii) depositing a second polysilicon layer over the semiconductor substrate including the first contact hole, and then patterning the same so as to form a second polysilicon film, (iii) depositing a second insulating film over the semiconductor substrate including the second polysilicon film, and then opening a second contact hole so as to form a second insulating film, (iv) depositing a third polysilicon layer over the semiconductor substrate including the second contact hole, and then patterning the same so as to form a third polysilicon film as a capacitor bottom electrode, (v) implanting ions in the second polysilicon film in a region other than a capacitor formation region so as to form a source/drain region, (vi) depositing a third insulating layer over the whole surface, and then opening a contact window so as to form a third insulating film as a capacitor insulating film, and (vii) depositing a fourth polysilicon layer over the semiconductor substrate including the contact window, and then patterning the same so as to make a fourth polysilicon film remain as a capacitor top electrode in only the capacitor formation region.

Inventors

  • 👤 Alberto Oscar Adan

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 21:18
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; F; F16; F16L; F16L53/00

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 229 words
A method for manufacturing a semiconductor apparatus, comprising steps of; (i) depositing a first insulating layer over a semiconductor substrate having a polysilicon gate formed by a first polysilicon film, and then opening a first contact hole so as to form a first insulating film, (ii) depositing a second polysilicon layer over the semiconductor substrate including the first contact hole, and then patterning the same so as to form a second polysilicon film, (iii) depositing a second insulating film over the semiconductor substrate including the second polysilicon film, and then opening a second contact hole so as to form a second insulating film, (iv) depositing a third polysilicon layer over the semiconductor substrate including the second contact hole, and then patterning the same so as to form a third polysilicon film as a capacitor bottom electrode, (v) implanting ions in the second polysilicon film in a region other than a capacitor formation region so as to form a source/drain region, (vi) depositing a third insulating layer over the whole surface, and then opening a contact window so as to form a third insulating film as a capacitor insulating film, and (vii) depositing a fourth polysilicon layer over the semiconductor substrate including the contact window, and then patterning the same so as to make a fourth polysilicon film remain as a capacitor top electrode in only the capacitor formation region.
Claim 2
Independent Claim 32 words
A method of manufacturing a semiconductor memory cell which comprises a plurality of thin film transistors formed on a semiconductor substrate, wherein the method includes forming a cross-coupling capacitor between cell nodes.
Claim 3
Dependent Claim 26 words
A method according to claim 2, said cross-coupling capacitor being stacked on top of the memory cell so as to avoid increase in the cell area.
Claim 4
Dependent Claim 15 words
A semiconductor apparatus in memory cell made by a method according to any preceding claim.

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