EP0475646A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit comprising interconnections
Assignee: Plessey Semiconductors Ltd
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Filing: 1991-08-30
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Granted: —
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Expires: 2011-08-30
Abstract
Abstract A semiconductor integrated circuit chip is provided comprising a substrate 1, a dielectric layer 3, deposited on the substrate 1 and one or more conductive tracks 4, 5 formed on the dielectric layer 3, at least part of the dielectric layer 3 which is along at least one edge of the conductive tracks 4, 5 and which is adjacent to the part of the dielectric layer 3 which underlies the conductive track 4, 5 being etched away to form an air gap 16 in the region where fringing fields and/or lateral fields exist, thereby to reduce the stray interconnection capacitance between the conductive tracks 4,5 and the substrate 1 (Figure 2). <IMAGE>
Inventors
- 👤 Peter Henry Saul
- 👤 Stephen James White
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 21:52
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/495
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
80 words
A semiconductor integrated circuit arrangement comprising a first conductive region, a dielectric layer disposed over said first conductive region and a conductive track disposed on said dielectric layer, in which at least part of the dielectric layer which is along at least one edge of said conductive track and which is adjacent to the part of the dielectric layer which underlies said conductive track is removed to reduce the interconnection capacitance between said conductive track and said first conductive region.
Claim 2
Dependent Claim
28 words
An arrangement as claimed in claim 1, in which part of the dielectric layer which underlies said conductive track is also removed to further reduce said interconnection capacitance.
Claim 3
Dependent Claim
25 words
An arrangement as claimed in claim 1 or claim 2, in which said first conductive region is constituted by the semiconductor substrate of said arrangement.
Claim 4
Dependent Claim
30 words
An arrangement as claimed in claim 1 or claim 2, in which said first conductive region is constituted by a further conductive track over which said dielectric layer is deposited.
Claim 5
Dependent Claim
24 words
An arrangement as claimed in any preceding claim, in which the said part of said dielectric layer which is removed is removed by etching.
Claim 6
Dependent Claim
27 words
An arrangement as claimed in claim 5, in which the said part of said dielectric layer which is removed by etching is defined by said conductive track.
Claim 7
Dependent Claim
24 words
An arrangement as claimed in any preceding claim, in which said conductive track is formed as part of a metallisation layer of said arrangement.
Claim 8
Dependent Claim
51 words
An arrangement as claimed in claim 7, in which said metallisation layer comprises a plurality of conductive tracks disposed substantially adjacent to one another, and in which the dielectric layer between said tracks is removed to reduce the interconnection capacitance therebetween and between said conductive tracks and said first conductive region.
Claim 9
Dependent Claim
22 words
An arrangement as claimed in claim 7 and claim 8, comprising a plurality of superposed metallisation layers separated by respective dielectric layers.
Claim 10
Dependent Claim
28 words
An arrangement as claimed in claim 9, in which at least part of each of the respective dielectric layers is removed in dependence upon said respective metallisation layers.
Claim 11
Independent Claim
83 words
A method of making a semiconductor integrated circuit arrangement comprising the steps of providing a first conductive region, depositing a dielectric layer over said first conductive region, providing a conductive track on said dielectric layer, and removing at least part of the dielectric layer which is along at least one edge of said conductive track and which is adjacent to the part of the dielectric layer which underlies said track, thereby reducing the interconnection capacitance between said conductive track and said conductive region.
References Cited (Backward Citations)
No citation records indexed.
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