EP0474245A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
•
Filing: 1991-09-06
•
Granted: —
•
Expires: 2011-09-06
Abstract
Abstract In a semiconductor memory device having a random access port for enabling data access at random and a serial access port for enabling data access in series, the transfer gate (15, 17) and the data register (16, 18) of the serial access memory port are divided into two systems, respectively. Therefore, data access operations are alternated in such a way that when data are transferred between one data register (16, 18) and the memory cell array (1), data are transferred between the other data register (16, 18) and an external device.
Inventors
- 👤 Hironori Doi
- 👤 Tatsuo Ikawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 16:16
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1075; G11C11/00; G11C11/21; G11C11/34; G11C11/40
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
339 words
A semiconductor memory device having a memory cell array (1) in which a plurality of memory cells are arranged into an M-row and N-column matrix form, characterized in that the semiconductor memory device comprises, (a) a random access memory port for enabling random data access, having a row decoder (2) for selecting any given row of the M rows of the memory cell array (1) and a column decoder (3) for selecting any given column of the N columns of the memory cell array (1); and (b) a serial access memory port for enabling serial data access, having: (1) a data register including a first data register (16) for holding an ℓ-bit data, where ℓ denotes an integer from 1 to N, and a second data register (18) for holding an (N-ℓ) bit data; (2) a transfer gate including a first transfer gate (15) for controlling data transfer between ℓ-piece memory cells of any given row selected by said row decoder (2) and said first data register (16) and a second transfer gate (17) for controlling data transfer between remaining (N-ℓ)-piece memory cells of the selected row and the second data register (18); (3) a serial selector including a first serial selector (19) for controlling data transfer between said first data register (16) and an external device and a second serial selector (20) for controlling data transfer between said second data register (18) and the external device; said first and second transfer gates (15, 17) controlling data transfer alternately, and said first and second serial selectors (19, 20) similarly controlling data transfer alternately; when said first transfer gate (15) is transferring data between the ℓ-piece memory cells and said first data register (16), said second serial selector (20) transfers data between said second data register (18) and the external device; and when said second transfer gate (17) is transferring data between the (N-ℓ) piece memory cells and said second data register (18), said first serial selector (19) transfers data between said first data register (16) and the external device.
Claim 2
Dependent Claim
28 words
The semiconductor memory device of claim 1, which further comprises means for displaying (12) which of said first and second data registers (16, 18) is effecting data access.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.