EP0473903A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Single phase clock distribution circuit for providing clock signals to multiple chip integrated circuit systems
Assignee: International Business Machines Corp
•
Filing: 1991-07-10
•
Granted: —
•
Expires: 2011-07-10
Abstract
Abstract A circuit to provide single phase clock signals having controlled clock skew to multiple integrated circuit chips is described. A source of single phase clock signals is supplied to a clock signal distribution tree of each integrated circuit. Phase comparison of signals produced by each clock distribution circuit tree provides a control signal for controlling the delay of a clock signal applied to a respective clock distribution tree. A gating circuit is disclosed which produces, in response to each clock signal produced by the clock distribution trees, an accurately controlled LOAD ENABLE and OUTPUT ENABLE signal.
Inventors
- 👤 Hu Herbert Chao
- 👤 Hung Herng Chang
- 👤 Feng-Hsien Warren Shih
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 06:50
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
156 words
A circuit for providing clocking signals to multiple chips which are phase-locked to reduce clock skew between integrated circuit chips comprising: a source of single phase clock signals for supplying a common clock signal to all of said integrated circuit chips; a clock distribution tree circuit at each integrated circuit chip for receiving a clock signal and distributing said signal to a plurality of register cells on an integrated circuit chip; a controllable delay line on each integrated circuit chip for controlling the delay of a clock signal received, and supplying said clock signal to said clock distribution tree; and, a phase detector on one of said integrated circuit chips for comparing the phase of a clock signal from one of said integrated circuit chips' clock distribution tree to a clock signal from another chip's clock distribution tree, and providing a signal to said controllable delay line to reduce the phase difference between compared clock signals.
Claim 2
Dependent Claim
35 words
The circuit of claim 1 further comprising a phase detector on a third integrated circuit chip for comparing said third chip clock distribution tree signal with a signal from said another chip clock distribution tree.
Claim 3
Dependent Claim
82 words
The circuit of claim 1 or 2 wherein each integrated circuit chip further comprises: first and second register circuits for receiving respective OUTPUT and LOAD signals for a respective register cell; and, a series of fixed delay circuits for receiving a clock signal from said clock distribution tree circuit and providing delayed clocking signals to said first and second register circuits, whereby a time delay is introduced between the generation of LOAD ENABLE and OUTPUT ENABLE signals produced by said register cell.
Claim 4
Dependent Claim
19 words
The circuit of claim 3 wherein said series of fixed delay circuits comprises a series of connected inverter circuits.
Claim 5
Dependent Claim
46 words
The circuit of claim 3 or 4 wherein said first register circuit comprises first and second gate transistors interconnected by a parallel combination of inverter circuits, said gate transistors having gate connections connected to receive said delayed clocking signals from said series of fixed delay circuits.
Claim 6
Dependent Claim
53 words
The circuit of one of claims 3 to 5 wherein said second register circuit comprises a gate transistor receiving an OUTPUT ENABLE control signal, and providing said OUTPUT ENABLE control signal to a pair of parallel connected inverter circuits in response to one of said delayed clock signals from said fixed delay circuits.
Claim 7
Dependent Claim
87 words
A circuit for providing from a command clock signal a clocked LOAD ENABLE signal and OUTPUT ENABLE signal to a register cell having a predetermined time difference comprising: a master-slave register for receiving a LOAD control signal, and passing a LOAD ENABLE signal to a register logic cell in response to first and second delayed clock signals; and, a single-level register for receiving an OUTPUT control signal, and passing an OUTPUT ENABLE signal to a second register logic cell in response to said second delayed clock signals.
Claim 8
Dependent Claim
26 words
The circuit of claim 7 wherein said delayed clock signals are provided by first and second inverter circuits serially connected to a source of clock signals.
Claim 9
Dependent Claim
29 words
The circuit of claim 8 wherein said source of clock signals comprises a clock distribution circuit which provides a clock signal for different circuits of an integrated circuit chip.
Claim 10
Dependent Claim
24 words
The circuit of claim 9 wherein said clock distribution circuit is coupled by a third inverter circuit to said first and second inverter circuits.
Claim 11
Dependent Claim
21 words
The circuit of claim 10 wherein said third inverter circuit supplies an inverted clock signal to said first register logic cell.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.