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EP0473421A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: NEC Corp
•
Filing: 1991-08-29
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Granted: —
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Expires: 2011-08-29
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Abstract

Abstract A semiconductor memory device is capable of holding stored contents of memory cells (MC) in a dynamic random access memory (DRAM) (101) effectively through a refresh operation. The memory device comprises a frequency-divider circuit (106), a refresh control circuit (105) for generating a word line activation signal (118) in response to an output of the frequency-divider circuit, and a control circuit (107) for controlling the frequency division value of the frequency-divider circuit. Even when switching directly after regular refreshing associated with read/write or other operation to self-refresh mode, as the first-time refreshing for all memory cells is performed at a higher restore level and at a shorter period than in regular refresh mode, the stored data of the memory cells can be refreshed at a low restore level.

Inventors

  • 👤 Toru c/o NEC Corporation Ishikawa

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-01 14:04
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 143 words
A semiconductor memory device comprising a frequency divider circuit for dividing selectively clock pulses in accordance with frequency-division control pulses; a frequency-division controller circuit for, upon reaching a specified count while counting said clock pulses in response to an control pulse input, changing frequency-division control pulses; refresh-address generating means for generating refresh addresses in response to said outputs of said frequency divider circuit; a refresh control circuit for generating word-line activating pulses in response to outputs of said frequency-divider circuit and said control pulse; a memory cell array unit including an array consisting of plurality of memory cellls and said bit and word lines each connected to a row or column of memory cells; and decode means for selecting in accordance with a refresh address said specified word line, and activating this selected word line in response to a word line activating signal.
Claim 2
Dependent Claim 39 words
A semiconductor memory device according to claim 1, wherein said frequency divider circuit comprises division means including a plurality of flip-flops and means for controlling the outputs of said frequency divider circuit in accordance with said frequency-division control pulses.
Claim 3
Dependent Claim 52 words
A semiconductor memory device according to claim 1, wherein said frequency-division controller circuit comprises counting means for, upon reaching a specified count while counting said clock pulses in response to said control pulse, generating a detection pulse; and control means for changing said frequency-division control pulses in response to said detection pulse.
Claim 4
Dependent Claim 35 words
A semiconductor memory device according to claim 1, wherein said frequency-division controller circuit comprises means for changing said frequency-division control pulse in response to a detection signal from a counter constituting said address generating means.
Claim 5
Dependent Claim 41 words
A semiconductor memory device according to claim 1 further comprising a selector for, in response to said control pulse, selecting either the output of said frequency divider circuit or refresh signal and provides the selected one to said address generating means.

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