EP0473314A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Peripheral data processing system control apparatus

Assignee: International Business Machines Corp

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Filing: 1991-08-09

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Granted: —

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Expires: 2011-08-09

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Abstract

Abstract A control unit (12) for DASD operation to transfer data between the device (13) and a buffer (16) and between a channel (11) and a buffer (16). In that manner the channel and device are enabled to transfer data independently of each other. Mechanisms are provided for communication between the channel interface process in the control unit and the device interface process in the control unit. Some of these mechanisms are stored with the record in the buffer and others are stored in control storage. Principle communicating mechanisms include a device record pointer, a channel record pointer, a next operation field, a device state indicator, record control flags, and two buffer pointers.

Inventors

👤 Brent Cameron Beardsley
👤 Keith Anthony Bello
👤 Michael Thomas Benhase
👤 Florence Joann Clark
👤 Paul Wayne Hunter
👤 Donald Marvin Nordahl

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-11-06 14:46

CPC Classifications

G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F3/0628; G06F3/0655; G06F3/0656

Claims Analysis

Total Claims: 4

Claim 1

Independent Claim 192 words

A data processing system including apparatus for controlling data transfer between a host processor in said data processing system and a data storage subsystem, said control apparatus comprising: buffer storage means for containing data intermediate to its transfer between said data storage subsystem and said host processor; a device interface processor for controlling data transfer between said data storage subsystem and said buffer; a channel interface processor for controlling data transfer between said host processor and said buffer; control storage associated with said device interface processor and said channel interface processor for providing a first record pointer for indicating the buffer address of a data record said device interface processor is currently processing and a second record pointer for indicating the buffer address of a data record said channel interface processor is currently processing; and means for preventing said channel interface processor overwriting a buffer address before data contained therein has been processed by said device interface processor during a write data transfer and means for preventing said device interface processor overwriting a buffer address before data contained therein has been processed by said channel interface processor during a read data transfer.

Claim 2

Dependent Claim 85 words

A data processing system as claimed in Claim 1 further comprising: next operating field indicating means for informing said device interface processor of the next command to be processed; means for signalling said device interface processor in a write data transfer operation, that said channel interface processor has loaded a count field for data to be transferred, set up said next operating field indicating means and has loaded said record pointers thereby preventing overwriting of a buffer address before data stored therein has been processed.

Claim 3

Dependent Claim 24 words

A data processing system as claimed in any of Claims 1 or 2 wherein said data storage subsystem includes a direct access storage device.

Claim 4

Dependent Claim 36 words

A data processing system as claimed in any of the preceding claims wherein data transfer between said host processor and said buffer is not synchronous with data transfer between said buffer and said data storage subsystem.

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