EP0472285A2
Expired / Lapsed
EP
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External memory access control for a processing system
Assignee: Advanced Micro Devices Inc
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Filing: 1991-07-17
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Granted: —
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Expires: 2011-07-17
Abstract
Abstract There is disclosed a processing system of the type having a processor which accesses external memory for data and/or instructions which includes an improved external memory access control system for rendering the external memory enable time durations independent from the number of external memory accesses per unit of time for reducing power consumption of the processing system. The control system includes clock means for providing a clock signal which determines the external memory access rate and enable duration control means coupled to the clock means which is arranged to enable the external memory for time durations during each memory access which are independent from the external memory access rate.
Inventors
- 👤 Dean Grumlose
- 👤 Dale Gulick
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 23:44
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/04; G06F1/3234; G06F1/325; G06F1/3275; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
122 words
In a processing system of the type having a processor which accesses external memory for data and/or instructions, an improved external memory access control system for rendering the external memory enable time durations independent from the number of external memory accesses per unit of time for reducing power consumption of said processor, said control system comprising: clock means for providing a clock signal for determining said number of external memory accesses per unit of time; and enable duration control means coupled to said clock means and being arranged to provide said external memory with external memory enable time duration control signals for establishing external memory enable time durations which are independent from said number of external memory accesses per unit of time.
Claim 2
Dependent Claim
122 words
In a processing system of the type having a processor which accesses external memory for data and/or instructions, an improved external memory access control system for rendering the external memory enable time durations independent from the number of external memory accesses per unit of time for reducing power consumption of said processor, said control system comprising: clock means for providing a clock signal for determining said number of external memory accesses per unit of time; and enable duration control means coupled to said clock means and being arranged to provide said external memory with external memory enable time duration control signals for establishing external memory enable time durations which are independent from said number of external memory accesses per unit of time.
Claim 3
Dependent Claim
62 words
A control system as defined in Claim 1 wherein said clock means includes a clock source having an output for providing a clock output and a divider having an input coupled to said clock source output and an output for providing said clock signal and wherein said enable duration control means has an input coupled between said clock source and said divider.
Claim 4
Dependent Claim
48 words
A control system as defined in Claim 2 wherein said divider output is arranged to provide external memory access rates including a fast rate and a slow rate and wherein said enable duration control means is arranged to provide the same enable time duration for both said rates.
Claim 5
Dependent Claim
24 words
A control system as defined in Claim 3 wherein said fast rate is on the order of thirty-two times greater than said slow rate.
Claim 6
Dependent Claim
18 words
A control system as defined in Claim 1 wherein said enable duration control means comprises a one-shot multivibrator.
Claim 7
Dependent Claim
82 words
A control system as defined in Claim 1 wherein said processing system comprises a plurality of external memories, wherein said processor includes a central processing unit for generating a first set of external memory addresses, and wherein said control system further comprises address decode logic means coupled to said central processing unit and to said external memories for providing memory select signals to said external memories responsive to said first set of external memory addresses for selecting the memories to be accessed.
Claim 8
Dependent Claim
47 words
A control system as defined in Claim 6 wherein said central processing unit is further arranged for generating a second set of external memory addresses and is coupled to each of said external memories for conveying said second set of external memory addresses to said external memories.
Claim 9
Dependent Claim
74 words
A control system as defined in Claim 7 wherein each of said external memories includes a plurality of memory locations, each said location having a unique address with respect to its external memory, wherein said memory select signals are arranged to select the external memory to be accessed and wherein said second set of external memory addresses are arranged to select the memory location to be accessed within said external memory to be accessed.
Claim 10
Dependent Claim
19 words
A control system as defined in Claim 6 wherein said address decode logic means are external to said processor.
Claim 11
Dependent Claim
18 words
A control system as defined in Claim 6 wherein said address decode logic means are within said processor.
Claim 12
Dependent Claim
55 words
A control system as defined in Claim 6 wherein said clock means includes a clock source and a divider, said clock source being coupled to said divider, said divider having an output for providing said clock signal and wherein said enable duration control means includes an input coupled between said clock source and said divider.
Claim 13
Dependent Claim
17 words
A control system as defined in Claim 11 wherein said clock source is external to said processor.
Claim 14
Dependent Claim
15 words
A control system as defined in Claim 12 wherein said divider is within said processor.
Claim 15
Dependent Claim
18 words
A control system as defined in Claim 13 wherein said access duration control means is within said processor.
Claim 16
Dependent Claim
44 words
A control system as defined in Claim 6 wherein said processing system includes a bus coupled between said central processing unit and said external memories for conveying said data or instructions between said central processing unit and said external memories during said memory accesses.
Claim 17
Dependent Claim
49 words
A control system as defined in Claim 15 wherein said enable duration control means include an output coupled to said external memories for providing said external memories with said external memory enable time duration control signals for enabling said memories to utilize said bus during said enable time durations.
Claim 18
Dependent Claim
22 words
A control system as defined in Claim 16 wherein said enable duration control means output is coupled directly to said external memories.
Claim 19
Dependent Claim
27 words
A control system as defined in Claim 16 wherein said enable duration control means output is coupled to said external memories through said address decode logic means.
Claim 20
Dependent Claim
90 words
A memory access control system for controlling the memory enable times of a memory independently from the memory access rate, said memory access control system comprising: clock means for providing memory access rates including a maximum rate and a slow rate; and memory enable duration control means having an input coupled to said clock means and an output coupled to said memory for providing said memory with enable signals having a fixed duration corresponding to said maximum access rate regardless of the memory access rate provided by said clock means.
Claim 21
Dependent Claim
90 words
A memory access control system for controlling the memory enable times of a memory independently from the memory access rate, said memory access control system comprising: clock means for providing memory access rates including a maximum rate and a slow rate; and memory enable duration control means having an input coupled to said clock means and an output coupled to said memory for providing said memory with enable signals having a fixed duration corresponding to said maximum access rate regardless of the memory access rate provided by said clock means.
Claim 22
Dependent Claim
64 words
A memory access control system as defined in Claim 19 wherein said clock means comprises a clock source for providing clock signals for establishing said maximum rate and a divider coupled to said clock source for dividing said clock signals for providing said slow rate, and wherein said memory enable duration control means has an input coupled between said clock source and said divider.
References Cited (Backward Citations)
No citation records indexed.
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