EP0471256A2
Expired / Lapsed
EP
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ATM switch and ATM multiplexer
Assignee: Hitachi Ltd
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Filing: 1991-08-02
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Granted: —
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Expires: 2011-08-02
Abstract
Abstract An ATM switch has a plurality of concentration space-division switches (9-16) each constituted with an S-stage connection of switch modules (84). Each of the switch modules includes M buffers (87-1 to 87-M) and a selector (89) for selecting an arbitrary one of outputs from the M buffers. Each stage includes switch modules of which the number is obtained by multiplying by at most M a number of switch modules disposed in a stage succeeding thereto. The S stages include a final stage constituted with a switch module. <IMAGE>
Inventors
- 👤 Masahiro Hitachi Daini Kyoshinryo Takatori
- 👤 Yukio Nakano
- 👤 Yoshihiro Ashi
- 👤 Tadayuki Kanno
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 14:43
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L49/00; H04L49/10; H04L49/104; H04L49/105; H04L49/106; H04L49/15; H04L49/1553; H04L49/25; H04L49/253; H04L49/255; H04L2012/5638; H04L2012/5646; H04L2012/5647; H04L2012/5672; H04L2012/5678; H04L2012/5681
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
233 words
An ATM switch of an individual buffer type accommodating K (K is an integer not less than one) input highways (80-1 to 80-K) and L (L is an integer not less than one) output highways (82-1 to 82-L) and including concentration space-division switches (9 to 16; 81-1 to 81-L) respectively for said output highways, each said concentration space-division switch having K inputs and an output and including switch modules (84) connected to each other in an S-stage structure (S is an integer not less than one), wherein each said switch module comprises: M buffers (87-1 to 87-M) respectively connected to M inputs (M is an integer not less than one); M buffer control circuit (88-1 to 88-M) for conducting write and read control operations respectively on said M buffers; a selector (89) for selecting an arbitrary one of outputs from said M buffers; and a selector control circuit (85) for issuing an output instruction to an arbitrary one of said buffer control circuits and for achieving a selector control operation associated therewith, each said stage including switch modules of which a number is obtained by multiplying by at most M a number of switch modules in a stage subsequent thereto, said S stages including a final stage constituted with one switch module, said M switch modules in each said stage having outputs connected to inputs of switch modules in a stage subsequent thereto.
Claim 2
Dependent Claim
206 words
An ATM multiplexer accommodating K (K is an integer not less than one) input highways (80-1 to 80-K) and S (L is an integer not less than one) output highways (82-1 to 82-L) and including switch modules being connected to each other in an S-stage structure (S is an integer not less than one) for each said output highways, wherein each said switch module comprises: M buffers (87-1 to 87-M) respectively connected to M inputs (M is an integer not less than one); M buffer control circuit (88-1 to 88-M) for conducting write and read control operations respectively on said M buffers; a selector (89) for selecting an arbitrary one of outputs from said M buffers; and a selector control circuit (85) for issuing an output instruction to an arbitrary one of said buffer control circuits and for achieving a selector control operation associated therewith, each said stage including switch modules of which a number is obtained by multiplying by at most M a number of switch modules in a stage subsequent thereto, said S stages including a final stage constituted with one switch module, said M switch modules in each said stage having outputs connected to inputs of switch modules in a stage subsequent thereto.
Claim 3
Dependent Claim
81 words
The device of Claim 1 or 2, wherein in case a cell loss is predicted due to a buffer overflow in either one of said switch modules, a read inhibit signal (72-1) is sent to switch modules in a stage immediately preceding the stage in which the cell loss is predicted such that, on receiving the read inhibit signal, the switch modules in the preceding stage stop transmitting a cell to the switch module in which the cell loss is predicted.
Claim 4
Independent Claim
70 words
The device of any of Claims 1 to 3, wherein M=2 and said two buffers of said switch module are accessed such that: cells are alternately read therefrom in an ordinary case; cells are sequentially read, when either one of said buffers is empty, from other one thereof; and cells are again sequentially read, when said buffers are both loaded with cells, from said two buffers in an alternate fashion.
Claim 5
Dependent Claim
182 words
An ATM switch of an individual buffer type having, in order to achieve a switching operation of asynchronously multiplexed cells between K (K being an integer not less than 1) input highways (80-1 to 80-K) and L (L being an integer not less than 1) output highways (2-1 to 82-L), concentration space-division switches (9 to 16; 81-1 to 81-L) respectively for said output highways, each said concentration space-division switch possessing K inputs and an output and including switch modules (84) connected to each other in an S-stage structure (S is an integer not less than one), each said switch module comprising buffer means (87-1 to 87-M) for multiplexing M inputs (M is an integer not less than one) into an output, each said stage including switch modules the number of which is obtained by multiplying the number of switch modules in a stage subsequent thereto by at most M, said S stages including a final stage constituted with one switch module, said M switch modules in each said stage having outputs connected to inputs of switch modules in a stage subsequent thereto.
Claim 6
Dependent Claim
145 words
An ATM multiplexer accommodating K (K is an integer not less than one) input highways (80-1 to 80-K) and L (L is an integer not less than one) output highways (82-1 to 82-L) and including switch modules (56, 57) being connected to each other in an S-stage structure (S is an integer not less than one), wherein each said switch module comprises: M inputs (M is an integer not less than one); and buffer means (52) for multiplexing said M inputs into an output, each said stage including switch modules the number of which is obtained by multiplying the number of switch modules in a stage subsequent thereto by at most M, said S stages including a final stage constituted with one switch module, said M switch modules in each said stage having outputs connected to inputs of switch modules in a stage subsequent thereto.
Claim 7
Dependent Claim
59 words
The device of Claim 5 or 6, wherein each said switch module comprises: a multiplexer (11;51) for multiplexing cells received from said M inputs through a cell interleaving operation; a buffer memory (12;52) for storing therein cells produced from said multiplexer; and a buffer memory control circuit (13;53) for issuing cell write and read instructions to said buffer memory.
Claim 8
Dependent Claim
50 words
The device of Claim 5 or 6, wherein each said switch module comprises: a buffer memory (31;59) having M inputs and an output for storing therein cells received from said M inputs; and a buffer memory control circuit (13;53) for issuing cell write and read instructions to said buffer memory.
Claim 9
Dependent Claim
80 words
The device of Claim 5 or 6, wherein, in case a number of cells loaded in either one of said switch modules exceeds a preset threshold value, a read inhibit signal (72-1) is sent to switch modules in a stage immediately preceding the stage in which the threshold value is exceeded such that,on receiving the read inhibit signal, the switch modules in the preceding stage stop transmitting a cell to the switch module in which the threshold value is exceeded.
Claim 10
Dependent Claim
47 words
The device of Claim 5 or 6, wherein said buffer memory of said switch module in the succeeding stage has a cell storage capacity equal to or more or less than a cell storage capacity of said buffer memory of said switch module in the preceding stage.
Claim 11
Independent Claim
17 words
The device of any of Claims 1 to 3 and 5 to 10, wherein M = 2.
Claim 12
Dependent Claim
41 words
The device of Claim 11, wherein, in case K = L = 2 S , the first stage includes 2 S-1 switch modules, the second stage includes 2 S-2 switch modules, ..., and the S-th stage includes one 2⁰ switch module.
Claim 13
Independent Claim
91 words
The device of any of Claims 1, 2,5 and 6, wherein, in case a cell loss has taken place due to a buffer overflow in either one of said switch modules, a retransmission request signal (72-1) is sent to switch modules in a state immediately preceding the stage related to the cell loss such that,on receiving the retransmission request signal, one of the switch modules having sent the discarded cell in the preceding stage retransmits a cell identical to the discarded cell to the switch module associated with the cell loss.
References Cited (Backward Citations)
No citation records indexed.
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