Scannable register with delay test capability

Claim 2

A scan-register having at least first and second data input ports (SYS_DATA, SCAN_IN), at least one data output port, and inputs for at least first, second, third and fourth control signals (SYS_CLK, M_LOAD, CLK_B, CLK_A), comprising: a) first means (12A, 12A′, 12A˝, 12A‴), having inputs coupled to the first and second data input ports for selectively storing data appearing on one of the said data input ports in accordance with the occurrence of a predefined combination of states of at least the first and second control signals; b) second means (10A, 10A′, 10A˝, 10A‴) having at least one input coupled to the second data input port for selectively storing data appearing on the second data input port in accordance with the occurrence of predefined state of at least the third control signals; and, c) third means (12B, 12B′, 12B˝, 12B‴) having at least one input port coupled to an output of at least one of the first and second means, and further having an output coupled to the data output port, for selectively storing data stored in one of the first and second means in accordance with the occurrence of a predefined state of at least the fourth control signal and providing the data stored therein to the data output port; the data appearing on one of the first and second data input ports being sequentially shiftable through selected ones of the first, second and third means, to the output port in accordance with the occurrence of predefined sequences of the predefined states of at least selected ones of the control signals.

Claim 3

Scan register according to claim 2, further comprising a disable input (D_STRB) coupled to the first means for disabling the first means from responding to the occurrence of the first control signals (SYS_CLK).

Claim 4

Scan register according to claim 2 wherein the third means has a pair of inputs (D,SIN), a first one of the inputs of the third means being coupled to an output (Q,QN) of the first means, a second one of the inputs of the third means being coupled to an output (Q,QN) of the second means, the third means storing the data stored in the first means in accordance with the occurrence of a predefined state of the first control signal and storing the data stored in the second means in accordance with the occurrence of a predefined state of the fourth control signal.

Claim 5

Scan register according to claim 2 or 4 wherein, in a first mode of operation selected in accordance with a first predefined sequence of predefined states of the control signals, data is sequentially shiftable from one of the first and second data input ports, through the first and third means to the output data port while different data is stored in the second means, and in a second mode of operation selected in accordance with a second predefined sequence of predefined states of the control signals, data is sequentially shiftable from the second data input port, through the second and third means to the output data port while different data is stored in the first means.

Claim 6

Scan register according to claim 5 wherein data is shifted from the first data input port to the data output port in response to sequential occurrences of the predefined states of the first control signal and wherein data is shifted from the second data input port to the data output port in response to the occurrence of the predefined state of the second control signal followed by the occurrence of the predefined state of the first control signal.

Claim 7

Scan register according to claim 5 wherein data is shifted from the second data input port, directly through only the second means and third means to the data output port in response to the occurrence of the predefined state of the third control signal followed by the occurrence of the predefined state of the fourth control signal.

Claim 8

Scan-register according to claim 2 wherein the scan-register comprises first and second data output ports and wherein the second means has a pair of inputs (D_SIN), a first one of the inputs of the second means being coupled to an output (Q,QN) of the first means, a second one of the inputs of the second means being coupled to the second data input port (SCAN_IN), an output of the second means being coupled to the first data output port, and further wherein the third means has an input (D) coupled to an output of the second means (Q,QN) and an output (Q,QN) coupled to the second data output port (SCAN_OUT), the third means storing data provided at the output of the second means in accordance with the occurrence of the fourth control signal.

Claim 9

Scan-register according to claim 8 wherein, in a first mode of operation selected in accordance with a first predefined sequence of the predefined states of the control signals, data is sequentially shiftable from one of the first and second input ports, through the first and second means to the first data output port and to the third means for storage in the third means and presentation at the second data output port, and wherein, in a second mode of operation selected in accordance with a second predefined sequence of the predefined states of the control signals, data is sequentially shiftable from one of the first and second data input ports, through only the first and second means to only the first data output port, while different data is stored in the third means.

Claim 10

Scan-register according to claim 9 wherein data is shifted from the first data input port to the first data output port in response to sequential occurrences of the predefined states of the first control signal, and wherein data is shifted from the second data input port to the first data output port in response to the occurrence of the predefined state of the second control signal followed by the occurrence of the predefined state of the first control signal.

Claim 11

Scan-register according to claim 10 wherein data is shifted from the second data input port, directly through only the second means and third means to the first and second data output ports in response to the occurrence of the predefined state of the third control signal followed by the occurrence of the predefined state of the fourth control signal.