EP0470371A2
Expired / Lapsed
EP
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Semiconductor device with input protection circuit of high withstand voltage
Assignee: Toshiba Corp
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Filing: 1991-07-05
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Granted: —
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Expires: 2011-07-05
Abstract
Abstract A semiconductor device equipped with an input protection circuit having a high withstand voltage and an improved reliability. The input protection circuit of the semiconductor device includes a gate insulation film (15a) provided on the semiconductor substrate (1) corresponding to a region between the source region (2a) and the drain region (2a), having a thickness greater than that of a gate insulation film in the FET of the semiconductor device, where one of the source region (2a) and the drain region (2a) is connected with an external input terminal (13) for the semiconductor device, while the gate electrode and the other one of the source region (2a) and the drain region (2a) are connected with a power source (12) for the semiconductor device.
Inventors
- 👤 Kazuhiko Kakizoe
- 👤 Hiroaki Murakami
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 10:20
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D30/00; H10D30/60; H10D30/791; H10D30/792; H10D30/601; H10D30/797; H10P; H10P32/00; H10P32/30; H10P32/302
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
127 words
An input protection circuit for a semiconductor device using a FET, comprising: a semiconductor substrate; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a gate insulation film provided on the semiconductor substrate corresponding to a region between the source region and the drain region, having a thickness greater than that of a gate insulation film in the FET of the semiconductor device; and a gate electrode provided on the gate insulation film; wherein one of the source region and the drain region is connected with an external input terminal for the semiconductor device, while the gate electrode and the other one of the source region and the drain region are connected with a power source for the semiconductor device.
Claim 2
Dependent Claim
127 words
An input protection circuit for a semiconductor device using a FET, comprising: a semiconductor substrate; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a gate insulation film provided on the semiconductor substrate corresponding to a region between the source region and the drain region, having a thickness greater than that of a gate insulation film in the FET of the semiconductor device; and a gate electrode provided on the gate insulation film; wherein one of the source region and the drain region is connected with an external input terminal for the semiconductor device, while the gate electrode and the other one of the source region and the drain region are connected with a power source for the semiconductor device.
Claim 3
Dependent Claim
20 words
The input protection circuit of claim 1, wherein the thickness of the gate insulation film is greater than 450 Å.
Claim 4
Dependent Claim
57 words
The input protection circuit of claim 1, further comprising an additional gate electrode provided inside the gate insulation film at such a position that the thickness of the gate insulation film between the additional gate electrode and the semiconductor substrate is greater than the thickness of the gate insulation film in the FET of the semiconductor device.
Claim 5
Dependent Claim
24 words
The input protection circuit of claim 3, wherein the gate electrode and the additional gate electrode is connected together inside the gate insulation film.
Claim 6
Dependent Claim
57 words
The input protection circuit of claim 3, further comprising an extra gate electrode provided inside the gate insulation film at such a position that the thickness of the gate insulation film between the extra gate electrode and the semiconductor substrate is greater than the thickness of the gate insulation film in the FET of the semiconductor device.
Claim 7
Dependent Claim
25 words
The input protection circuit of claim 5, wherein the extra gate electrode and the additional gate electrode is connected together inside the gate insulation film.
Claim 8
Dependent Claim
50 words
The input protection circuit of claim 1, further comprising low impurity concentration diffusion layer regions provided adjacent to the source region and the drain region at portions underneath the gate insulation film corresponding to intervals between the gate electrode and each one of the source region and the drain region.
Claim 9
Dependent Claim
23 words
The input protection circuit of claim 1, wherein the source region and the drain region are formed to have a high impurity concentration.
Claim 10
Dependent Claim
27 words
The input protection circuit of claim 8, wherein the impurity concentration of the source region and the drain region is greater than 1 x 10 20 cm-3.
Claim 11
Dependent Claim
44 words
The input protection circuit of claim 1, wherein the semiconductor substrate, source region, and drain region form a bipolar transistor configuration with the semiconductor substrate as a base region, the source region as an emitter region, and the drain region as a collector region.
Claim 12
Dependent Claim
45 words
The input protection circuit of claim 1, wherein the semiconductor device also includes a high withstand voltage FET, and the thickness of the gate insulation film is equal to that of a gate insulation film of the high withstand voltage FET of the semiconductor device.
Claim 13
Dependent Claim
25 words
The input protection circuit of claim 11, wherein the input protection circuit has a gate structure identical to that of the high withstand voltage FET.
Claim 14
Dependent Claim
127 words
A semiconductor device, comprising: a FET; and an input protection device, including: a semiconductor substrate; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a gate insulation film provided on the semiconductor substrate corresponding to a region between the source region and the drain region, having a thickness greater than that of a gate insulation film in the FET of the semiconductor device; and a gate electrode provided on the gate insulation film; wherein one of the source region and the drain region is connected with an external input terminal for the semiconductor device, while the gate electrode and the other one of the source region and the drain region are connected with a power source for the semiconductor device.
Claim 15
Dependent Claim
127 words
A semiconductor device, comprising: a FET; and an input protection device, including: a semiconductor substrate; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a gate insulation film provided on the semiconductor substrate corresponding to a region between the source region and the drain region, having a thickness greater than that of a gate insulation film in the FET of the semiconductor device; and a gate electrode provided on the gate insulation film; wherein one of the source region and the drain region is connected with an external input terminal for the semiconductor device, while the gate electrode and the other one of the source region and the drain region are connected with a power source for the semiconductor device.
Claim 16
Dependent Claim
19 words
The semiconductor device of claim 13, wherein the thickness of the gate insulation film is greater than 450 Å.
Claim 17
Dependent Claim
56 words
The semiconductor device of claim 13, further comprising an additional gate electrode provided inside the gate insulation film at such a position that the thickness of the gate insulation film between the additional gate electrode and the semiconductor substrate is greater than the thickness of the gate insulation film in the FET of the semiconductor device.
Claim 18
Dependent Claim
23 words
The semiconductor device of claim 15, wherein the gate electrode and the additional gate electrode is connected together inside the gate insulation film.
Claim 19
Dependent Claim
56 words
The semiconductor device of claim 15, further comprising an extra gate electrode provided inside the gate insulation film at such a position that the thickness of the gate insulation film between the extra gate electrode and the semiconductor substrate is greater than the thickness of the gate insulation film in the FET of the semiconductor device.
Claim 20
Dependent Claim
24 words
The semiconductor device of claim 17, wherein the extra gate electrode and the additional gate electrode is connected together inside the gate insulation film.
Claim 21
Dependent Claim
50 words
The semiconductor device of claim 13, further comprising low impurity concentration diffusion layer regions provided adjacent to the source region and the drain region at portions underneath the gate insulation film corresponding to the intervals between the gate electrode and each one of the source region and the drain region.
Claim 22
Dependent Claim
22 words
The semiconductor device of claim 13, wherein the source region and the drain region are formed to have a high impurity concentration.
Claim 23
Dependent Claim
26 words
The semiconductor device of claim 20, wherein the impurity concentration of the source region and the drain region is greater than 1 x 10 20 cm-3.
Claim 24
Dependent Claim
43 words
The semiconductor device of claim 13, wherein the semiconductor substrate, source region, and drain region form a bipolar transistor configuration with the semiconductor substrate as a base region, the source region as an emitter region, and the drain region as a collector region.
Claim 25
Dependent Claim
41 words
The semiconductor device of claim 13, further including a high withstand voltage FET, where the thickness of the gate insulation film of the input protection circuit is equal to that of a gate insulation film of the high withstand voltage FET.
Claim 26
Dependent Claim
24 words
The semiconductor device of claim 23, wherein the input protection circuit has a gate structure identical to that of the high withstand voltage FET.
References Cited (Backward Citations)
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