Phase demodulator for psk-modulated signals

Claim 2

A phase demodulator of the differential detection type comprising: zero-cross detecting means for detecting, from a PSK signal transmitted over a transmission path, a zero-cross point at which the amplitude of this PSK signal crosses the reference voltage, and generating a zero-cross point indicating signal; sampling means for receiving at its input end a baud timing signal together with said zero-cross point indicating signal, and generating a synchronous baud timing signal synchronized with said zero-cross point indicating signal; a ring oscillator comprising N (N is a natural number) delay elements connected in a ring form and providing a delay time varying in response to a control signal, and having tap outputs, each pair of mutually adjoining output ends having a phase difference of 2 1 t/N, and an oscillating frequency substantially equal to the carrier frequency of said PSK signal; latching means for latching each of said tap outputs at the logical level varying point of said synchronous baud timing signal, and generating latch outputs, each corresponding to one or another of said N tap outputs; and an encoder for detecting in each baud period the logical level varying point at which the logical level varies between each pair of mutually adjoining ones among sequentially arranged said N latch outputs, and encoding information on these logical level varying points.

Claim 3

A phase demodulator, as claimed in Claim 1, further including: a reference phase oscillator for generating a reference phase signal whose frequency is approximately equal to the carrier frequency of said PSK signals; phase comparator means responsive to the phase difference between the oscillation output from the output end of one of the delay elements of said ring oscillator and said reference phase signal for generating a phase error signal; and a loop filter for smoothing said phase error signal into a delay control signal, wherein the oscillation frequency of said ring oscillator is made identical with said reference phase signal by using said delay control signal.

Claim 4

A phase demodulator, as claimed in Claim 1, wherein said zero-cross point indicating signal has a certain amplitude in one of the periods in which the amplitude of said PSK signal is positive or negative and has no amplitude in the other period.

Claim 5

A phase demodulator, as claimed in Claim 1, wherein said sampling means includes a flip-flop circuit which receives said zero-cross point indicating signal as a clock signal and said baud timing signal as its data input, and generates said synchronous baud timing signal as its data output.

Claim 6

A phase demodulator, as claimed in Claim 1, wherein said ring oscillator has an odd number of inverters connected in a ring form and said tap output is supplied from the output end of each of these inverters.

Claim 7

A phase demodulator, as claimed in Claim 2, wherein said ring oscillator has an odd number of inverters connected in a ring form and said tap output is supplied from the output end of each of said inverters.

Claim 8

A phase demodulator, as claimed in Claim 6, wherein the power supply terminal of each of said inverters also serves as an input terminal for said delay control signal.

Claim 9

A phase demodulator, as claimed in Claim 1, wherein said latching means includes N flip-flop circuits which receive said synchronous baud timing signal as a clock signal and one of said tap outputs as said data input, and generate each output of said latching means as data output.

Claim 10

A phase demodulator, as claimed in Claim 1, wherein said encoder includes means for detecting said logical level varying point in each of said baud periods and supplying the results of the detection, converted into digital signals; a subtracter for subtracting from said digital signal of a first baud period said digital signal of a second baud period following the first; and a decision circuit for determining the phase region of the output of said subtracter.

Claim 11

A phase demodulator, as claimed in Claim 2, wherein said encoder includes means for detecting said logical level varying point in each of said baud periods and supplying the phase information represented by those logical level varying points, converted into digital signals; a subtracter for subtracting from said digital signal of a first baud period said digital signal of a second baud period following the first; and a decision circuit for determining the phase region of the output of said subtracter.

Claim 12

A phase demodulator of the synchronous detection type comprising: zero-cross detecting means for detecting, from a PSK signal transmitted over a transmission path, a zero-cross point at which the amplitude of this PSK signal crosses the reference potential, and generating a zero-cross point indicating signal; sampling means for receiving at its input end a baud timing signal together with said zero-cross point indicating signal, and generating a synchronous baud timing signal synchronized with said zero-cross point indicating signal; a ring oscillator comprising N (N is a natural number) delay elements connected in a ring form and providing a delay time varying in response to a control signal, and having tap outputs, each pair of mutually adjoining output ends having a phase difference of 2 1 t/N, and an oscillating frequency substantially equal to the carrier frequency of said PSK signal; latching means for latching each of said tap outputs at the logical level varying point of said synchronous baud timing signal, and generating latch outputs, each corresponding to one or another of said N tap outputs; means for detecting in each of said baud periods said logical level varying point, and converting phase information represented by said logical level varying points into digital signals; a subtracter for subtracting from said digital signal representing said phase information of a first baud period said digital signal representing said phase information of a second baud period following the first; a decision circuit for determining the phase region of the output of said subtracter; and means for generating from each of said digital signals representing said phase information an offset signal representing the phase error of that signal.

Claim 13

A phase demodulator of the synchronous detection type comprising: zero-cross detecting means for detecting, from a PSK signal transmitted over a transmission path, a zero-cross point at which the amplitude of this PSK signal crosses the reference potential, and generating a zero-cross point indicating signal; sampling means for receiving at its input end a baud timing signal together with said zero-cross point indicating signal, and generating a synchronous baud timing signal synchronized with said zero-cross point indicating signal; a ring oscillator comprising N (N is a natural number) delay elements connected in a ring form and providing a delay time varying in response to a control signal, and having tap outputs, each pair of mutually adjoining output ends having a phase difference of 2 1 t/N, and an oscillating frequency substantially equal to the carrier frequency of said PSK signal; latching means for latching each of said tap outputs at the logical level varying point of said synchronous baud timing signal, and generating latch outputs, each corresponding to one or another of said N tap outputs; means for detecting in each of said baud periods said logical level varying point, and converting phase information represented by said logical level varying points into digital signals; a subtracter for subtracting from said digital signal representing said phase information of a first baud period said digital signal representing said phase information of a second baud period following the first; a decision circuit for determining the phase region of the output of said subtracter; and means for generating from each of said digital signals representing said phase information an offset signal representing the phase error of that signal.

Claim 14

A phase demodulator, as claimed in Claim 11, further including: a reference phase oscillator for generating a reference phase signal whose frequency is approximately M (M is a natural number including 1) times the carrier frequency of said PSK signals; phase comparator means responsive to the phase difference between the oscillation output from the output end of one of the delay elements of said ring oscillator and said reference phase signal for generating a phase error signal; and a loop filter for smoothing said phase error signal into a delay control signal, wherein the oscillation frequency of said ring oscillator is made identical with said reference phase signal by using said delay control signal.

Claim 15

A phase demodulator, as claimed in Claim 11, wherein said zero-cross point indicating signal has a certain amplitude in one of the periods in which the amplitude of said PSK signal is positive or negative and has no amplitude in the other period.

Claim 16

A phase demodulator, as claimed in Claim 11, wherein said sampling means includes a flip-flop circuit which receives said zero-cross point indicating signal as a clock signal and said baud timing signal as its data input, and generates said synchronous baud timing signal as its data output.

Claim 17

A phase demodulator, as claimed in Claim 11, wherein said ring oscillator has an odd number of inverters connected in a ring form and said tap output is supplied from the output end of each of these inverters.

Claim 18

A phase demodulator, as claimed in Claim 12, wherein said ring oscillator has an odd number of inverters connected in a ring form and said tap output is supplied from the output end of each of said inverters.

Claim 19

A phase demodulator, as claimed in Claim 16, wherein the power supply terminal of each of said inverters also serves as an input terminal for said delay control signal.

Claim 20

A phase demodulator, as claimed in Claim 11, wherein said latching means includes N flip-flop circuits which receive said synchronous baud timing signal as a clock signal and one of said tap outputs as said data input, and generate each output of said latching means as data output.

Claim 21

A phase demodulator, as claimed in Claim 11, wherein said offset signal generating means includes a multiplier for multiplying the output of said subtracter by the number of modulated phases of said PSK signals into a phase error signal; a loop filter for smoothing said phase error signal into a frequency control signal; and a numerical control oscillator for generating said offset signal by integrating said frequency control signal.

Claim 22

A phase demodulator, as claimed in Claim 12, wherein said offset signal generating means includes a multiplier for multiplying the output of said subtracter by the number of modulated phases of said PSK signals into a phase error signal; a loop filter for smoothing said phase error signal into a frequency control signal; and a numerical control oscillator for generating said offset signal by integrating said frequency control signal.