Security circuit for protecting data stored in an internal memory of a microcomputer

Claim 2

A security circuit for protecting data which are stored in an internal memory of a microcomputer, comprising first memory means (2) for storing a security code which is inputted from external; latch means (4) for latching a key code which is inputted in order to read said data that are stored in said internal memory; comparator means (6) for comparing whether or not said security code that is stored in said first memory means (2) and said key code that is latched by said latch means (4) are in agreement, and for outputting comparison results; second memory means (12) for storing said comparison results compared by said comparator means (6); and read control means (20) that uses said comparison results stored in said second memory means as the basis to prohibit read of data stored in said internal memory when said security code and said key code are not in agreement, and that uses an output control signal that is inputted from external when there is agreement as the basis to control read of data that is stored in said internal memory.

Claim 3

The security circuit according to claim 1, wherein said first and second memory means (2, 12) are each comprised of an electrically programmable read only memory (EPROM) of a non-volatile memory.

Claim 4

The security circuit according to claim 1, wherein said security circuit is connected with a data bus for transferring said security code to said first memory means (2) and said key code to said latch means (4), respectively.

Claim 5

The security circuit according to claim 1, further comprising an address decoder (30) which is connected with an address bus and supplies to said first memory means (2) a signal for directing write of said security code, and to said latch means (4) a signal for directing latch of said key code, respectively.

Claim 6

The security circuit according to claim 1, further comprising a set-reset flip-flop (8) that said signal for directing latch for said key code to said latch means (4) is inputted to a set terminal (S) thereof, and that an external reset signal is inputted to a reset terminal (R) thereof.

Claim 7

The security circuit according to claim 1, comprising a data bus for transferring said security code and said key code, which are inputted from an input device; an address bus for transferring address data which are inputted from said input device; a first EPROM (2) of non-volatile for storing said security code which is inputted through said data bus; a latch circuit (4) for latching said key code which is inputted by user through said input device in order to read out said data which are stored in said internal memory and inputted through said data bus; a comparator circuit (6) for comparing whether or not there is agreement between said security code stored in said first EPROM (2) and said key code latched by said latch circuit (4); an address decoder (30) for generating a signal (Si) which causes said first EPROM (2) to store said security code and a signal(S 2 ) which causes said latch circuit (4) to store said key code, responding to said address data which are inputted through said address bus; a set-reset flip-flop (8) which has a reset terminal (R) to which an external reset signal is inputted, and a set terminal (S) to which a signal from said address decoder (30) is inputted; a second EPROM (12) of non-volatile for storing said comparison results responding to an output from said flip-flop (8), when said comparison results of said comparator circuit (6) becomes agreement; and a read control circuit (20), on the basis of said comparison results stored in said second EPROM (12), for prohibiting the read of data stored in said internal memory when there is no agreement between said security code and said key code, and for enabling to read out said data stored in said internal memory in accordance with an output control signal which is inputted from external when there is agreement between said security code and said key code.