EP0467152A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Microprocessor capable of decoding two instructions in parallel
Assignee: Hitachi Ltd
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Filing: 1991-07-03
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Granted: —
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Expires: 2011-07-03
Abstract
Abstract An instruction fetch unit IU in a microprocessor capable of decoding two instructions in parallel fetches first and second instructions of the shortest instructions in one cycle. The fetched first instruction is supplied to and decoded by a first instruction decoder IDO, while the fetched second instruction is supplied to and decoded by a second instruction decoder ID1. In a case where an instruction having a bit width longer than the shortest instruction has been fetched by the instruction fetch unit IU, information to be decoded by the second instruction decoder ID1 is the non-head code of the instruction, and hence, a pipeline control unit PCNT invalidates the decoded result of the second instruction decoder ID1. Thus, it is permitted to decode the two shortest instructions in parallel, and to eliminate the erroneous information of the decoded result of the second decoder in the case of the fetch of the non-shortest instruction.
Inventors
- 👤 Susumu Narita
- 👤 Fumio Arakawa
- 👤 Tetsuhiko Okada
- 👤 Kunio Uchiyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 07:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/30; G06F9/38; G06F9/3818; G06F9/3822; G06F9/30145; G06F9/30149; G06F9/3016; G06F9/30167; G06F9/3867
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
314 words
A microprocessor comprising: a fetch unit which fetches first and second instructions each having an instruction length of predetermined bit width, from outside said microprocessor, and which delivers the first and second instructions to output lines in parallel, said output lines having a bit width that is at least double the predetermined width; a first instruction decoder whose input is supplied with the first instruction on said output lines of said fetch unit; a second instruction decoder whose input is supplied with the second instruction on said output lines of said fetch unit; a control unit which is supplied with a decoded result of said first instruction decoder and that of said second instruction decoder; and an instruction execution unit which responds to an output from said control unit; wherein under a condition under which the first instruction of the predetermined instruction length is delivered from said output lines having the bit width that is at least double the predetermined width, said control unit responds to information on fulfillment of the condition in the decoded result of said first instruction decoder and validates the decoded result of said second instruction decoder, so that said instruction execution unit executes the first instruction and the second instruction in parallel in response to the decoded results of said first and second instruction decoders transmitted as the output of said control unit; whereas under another condition under which an instruction having an instruction length different from the predetermined bit width is delivered from said output lines of said fetch unit, said control unit responds to information on fulfillment of the other condition in the decoded result of said first decoder and invalidates the decoded result of said second decoder, so that said instruction execution unit executes the first instruction in response to the decoded result of said first instruction decoder transmitted as the output of said control unit.
Claim 2
Dependent Claim
314 words
A microprocessor comprising: a fetch unit which fetches first and second instructions each having an instruction length of predetermined bit width, from outside said microprocessor, and which delivers the first and second instructions to output lines in parallel, said output lines having a bit width that is at least double the predetermined width; a first instruction decoder whose input is supplied with the first instruction on said output lines of said fetch unit; a second instruction decoder whose input is supplied with the second instruction on said output lines of said fetch unit; a control unit which is supplied with a decoded result of said first instruction decoder and that of said second instruction decoder; and an instruction execution unit which responds to an output from said control unit; wherein under a condition under which the first instruction of the predetermined instruction length is delivered from said output lines having the bit width that is at least double the predetermined width, said control unit responds to information on fulfillment of the condition in the decoded result of said first instruction decoder and validates the decoded result of said second instruction decoder, so that said instruction execution unit executes the first instruction and the second instruction in parallel in response to the decoded results of said first and second instruction decoders transmitted as the output of said control unit; whereas under another condition under which an instruction having an instruction length different from the predetermined bit width is delivered from said output lines of said fetch unit, said control unit responds to information on fulfillment of the other condition in the decoded result of said first decoder and invalidates the decoded result of said second decoder, so that said instruction execution unit executes the first instruction in response to the decoded result of said first instruction decoder transmitted as the output of said control unit.
Claim 3
Dependent Claim
58 words
A microprocessor according to claim 1, wherein when said control unit invalidates the decoded result of said second decoder, said instruction execution unit determines an address of an operand in response to that bit information of said output lines of said fetch unit which corresponds to a bit position of the invalidated decoded result of said second decoder.
Claim 4
Dependent Claim
16 words
A microprocessor according to claim 1, wherein the predetermined bit width is the shortest instruction length.
Claim 5
Dependent Claim
119 words
A microprocessor according to claim 1, wherein said control unit includes a selector, one input and the other input of which are respectively supplied with the decoded result of said second instruction decoder and a non-execution command instruction, and a control input of which is supplied with information indicating the fulfillment of the first-mentioned condition and the fulfillment of the other condition, wherein when the first-mentioned condition is fulfilled, the decoded result of said second instruction decoder is transmitted to an output of said selector, wherein when the other condition is fulfilled, the non-execution command instruction is transmitted to said output of said selector, and wherein the output signal of said selector is supplied to said instruction execution unit.
References Cited (Backward Citations)
No citation records indexed.
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